This patch fixes a few typos with computing registers to save/restore in prologue/epilogue. This fixes the github riscv/riscv-gcc issue #111. The typos are harmless, as these registers are call clobbered, but this was a problem for one person modifying gcc for academic reasons, and hence the typos need to be fixed.
Tested with a gcc make check, there were no regressions. Committed. gcc/ * config/riscv/riscv.c (riscv_for_each_saved_reg): Use GP_REG_LAST instead of GP_REG_LAST-1. (riscv_adjust_libcall_cfi_prologue): Likewise. (riscv_adjust_libcall_cri_epilogue): Likewise. * config/riscv/riscv.h (CALL_USED_REGISTERS): Change a6 to t6 in comment. --- gcc/config/riscv/riscv.c | 6 +++--- gcc/config/riscv/riscv.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 5547d68..c7283d0 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -3336,7 +3336,7 @@ riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset, riscv_save_restore_fn fn) /* Save the link register and s-registers. */ offset = cfun->machine->frame.gp_sp_offset - sp_offset; - for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST-1; regno++) + for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) { riscv_save_restore_reg (word_mode, regno, offset, fn); @@ -3424,7 +3424,7 @@ riscv_adjust_libcall_cfi_prologue () int saved_size = cfun->machine->frame.save_libcall_adjustment; int offset; - for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST-1; regno++) + for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) { /* The save order is ra, s0, s1, s2 to s11. */ @@ -3552,7 +3552,7 @@ riscv_adjust_libcall_cfi_epilogue () dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx, dwarf); - for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST-1; regno++) + for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) { reg = gen_rtx_REG (SImode, regno); diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index fe09e84..feada72 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -233,7 +233,7 @@ along with GCC; see the file COPYING3. If not see 1, 1 \ } -/* a0-a7, t0-a6, fa0-fa7, and ft0-ft11 are volatile across calls. +/* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls. The call RTLs themselves clobber ra. */ #define CALL_USED_REGISTERS \ -- 2.7.4