Thank you very much for fixing those issues. Note, __builtin_ia32_vpshufbitqmb{128,256,512}_mask are implemented > incorrectly, can somebody from Intel handle that? The inlines in the > intrinsic header look correct, but the builtins aren't and what's even worse > is that the define_insns are wrong too. According to the documentation > and inline fn, the intrinsics have an __mmask{16,32,64} input mask and > also __mmask{16,32,64} output mask. The builtins use > UHI_FTYPE_V2DI_V2DI_UHI > USI_FTYPE_V4DI_V4DI_USI > UQI_FTYPE_V8DI_V8DI_UQI > types (first two are correct, the last one is wrong, should have been > UDI_FTYPE_V8DI_V8DI_UDI), and the define_insn has: > (set (match_operand:QI 0 ("register_operand") ("=Yk")) > (and:QI (unspec:QI [ > (match_operand:V2DI 1 ("register_operand") ("v")) > (match_operand:V2DI 2 ("nonimmediate_operand") ("vm")) > ] 214) > (match_operand:QI 3 ("register_operand") ("Yk")))) > (incorrect, should use :HI result and :HI mask input), > (set (match_operand:QI 0 ("register_operand") ("=Yk")) > (and:QI (unspec:QI [ > (match_operand:V4DI 1 ("register_operand") ("v")) > (match_operand:V4DI 2 ("nonimmediate_operand") ("vm")) > ] 214) > (match_operand:QI 3 ("register_operand") ("Yk")))) > (incorrect, should use :SI result and :SI mask input), > (set (match_operand:QI 0 ("register_operand") ("=Yk")) > (and:QI (unspec:QI [ > (match_operand:V8DI 1 ("register_operand") ("v")) > (match_operand:V8DI 2 ("nonimmediate_operand") ("vm")) > ] 214) > (match_operand:QI 3 ("register_operand") ("Yk")))) > (incorrect, should use :DI result and :DI mask input). Similarly the > non-masked patterns, where just the result is incorrect, not the operand 3 > which doesn't exist). I'll file a PR to track this.
I'll fix that. Thanks, Julia > -----Original Message----- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Jakub Jelinek > Sent: Friday, December 22, 2017 7:40 PM > To: Kirill Yukhin <kirill.yuk...@gmail.com>; Uros Bizjak <ubiz...@gmail.com> > Cc: Koval, Julia <julia.ko...@intel.com>; GCC Patches <gcc- > patc...@gcc.gnu.org> > Subject: [PATCH] Fix various x86 avx512{bitalg,vpopcntdq,vbmi2} issues (PR > target/83488) > > On Fri, Dec 22, 2017 at 03:38:03PM +0300, Kirill Yukhin wrote: > > Hello, Julia, > > On 12 Nov 12:51, Koval, Julia wrote: > > > Hi, this patch enables AVX512BITALG and AVX512VPOPCNTDQ instructions > from > https://software.intel.com/sites/default/files/managed/c5/15/architecture- > instruction-set-extensions-programming-reference.pdf. Ok for trunk? > > OK for trunk. I've checked it in. > > Unfortunately, there are various issues in this patch as well as earlier > vbmi2 support. > > 1) as for various AVX512BITALG and AVX512VPOPCNTDQ builtins we need not > just > that ISA, but also AVX512VL or AVX512BW or both, these two ISAs need to be > moved over from ix86_isa_flags2 to ix86_isa_flags. > 2) while the PDF doesn't say that explicitly, for builtins that map to > hw insns that don't have AVX512BW listed as CPUID, if they use (or set) > 32-bit or 64-bit %k? mask register, we need AVX512BW for the builtin, > because otherwise we get ICEs when LRA is trying to load (or store) the > 32-bit or 64-bit %k? mask register. Most of the intrin*.h headers got the > requirements right (but see below), but not i386-builtins.def, so using > intrin headers was fine, but using builtins directly resulted in numerous > ICEs. > 3) some builtins where the define_insns were requiring AVX512VL didn't have > that requirement on the builtins, so again, numerous ICEs when using the > builtins directly. > 4) for some builtins the intrin headers were uselessly requiring avx512bw > even when it wasn't needed at all (either when they don't have any mask > argument or when they have an 8-bit or 16-bit only mask). > 5) the def_builtin/ix86_expand_builtin stuff didn't handle > OPTION_MASK_ISA_something | OPTION_MASK_ISA_AVX512BW or > OPTION_MASK_ISA_something | OPTION_MASK_ISA_AVX512VL | > OPTION_MASK_ISA_AVX512BW > right (while the VL is handled there as "require the other ISAs and VL", > for BW we don't do that). There were some hacks for GFNI and VPCLMULQDQ, > but incomplete and I think it is far better to treat BW and F like VL > instead of those 2. Plus we can improve stuff in def_builtin by only doing > this special handling if the whole mask isn't a single bit mask, then there > is no reason for just not requiring the isa. > 6) in i386-common.c I've noticed a major problem, for the new avx512 > extensions that live in flags2 rather than flags (after this patch it is > just avx5124fmaps and avx512vnniw), doing say -mavx5124fmaps -mno-avx512f > would properly disable -mavx5124fmaps, but doing -mavx5124fmaps -mno-avx2 > or -mavx5124fmaps -mno-sse etc. would not, again leading to numerous ICEs. > > Starting bootstrap/regtest on x86_64-linux and i686-linux right now, ok for > trunk if it passes? > > Note, __builtin_ia32_vpshufbitqmb{128,256,512}_mask are implemented > incorrectly, can somebody from Intel handle that? The inlines in the > intrinsic header look correct, but the builtins aren't and what's even worse > is that the define_insns are wrong too. According to the documentation > and inline fn, the intrinsics have an __mmask{16,32,64} input mask and > also __mmask{16,32,64} output mask. The builtins use > UHI_FTYPE_V2DI_V2DI_UHI > USI_FTYPE_V4DI_V4DI_USI > UQI_FTYPE_V8DI_V8DI_UQI > types (first two are correct, the last one is wrong, should have been > UDI_FTYPE_V8DI_V8DI_UDI), and the define_insn has: > (set (match_operand:QI 0 ("register_operand") ("=Yk")) > (and:QI (unspec:QI [ > (match_operand:V2DI 1 ("register_operand") ("v")) > (match_operand:V2DI 2 ("nonimmediate_operand") ("vm")) > ] 214) > (match_operand:QI 3 ("register_operand") ("Yk")))) > (incorrect, should use :HI result and :HI mask input), > (set (match_operand:QI 0 ("register_operand") ("=Yk")) > (and:QI (unspec:QI [ > (match_operand:V4DI 1 ("register_operand") ("v")) > (match_operand:V4DI 2 ("nonimmediate_operand") ("vm")) > ] 214) > (match_operand:QI 3 ("register_operand") ("Yk")))) > (incorrect, should use :SI result and :SI mask input), > (set (match_operand:QI 0 ("register_operand") ("=Yk")) > (and:QI (unspec:QI [ > (match_operand:V8DI 1 ("register_operand") ("v")) > (match_operand:V8DI 2 ("nonimmediate_operand") ("vm")) > ] 214) > (match_operand:QI 3 ("register_operand") ("Yk")))) > (incorrect, should use :DI result and :DI mask input). Similarly the > non-masked patterns, where just the result is incorrect, not the operand 3 > which doesn't exist). I'll file a PR to track this. > > 2017-12-22 Jakub Jelinek <ja...@redhat.com> > > PR target/83488 > * config/i386/i386.opt (-mavx512vpopcntdq, -mmavx512bitalg): Move > from > ix86_isa_flags2 to ix86_isa_flags. > * config/i386/i386-c.c (ix86_target_macros_internal): Test > OPTION_MASK_ISA_AVX512BITALG and > OPTION_MASK_ISA_AVX512VPOPCNTDQ in > isa_flags rather than isa_flags2. > * config/i386/i386.c (ix86_target_string): Move -mavx512vpopcntdq > and -mavx512bitalg from isa2_opts to isa_opts. > (ix86_option_override_internal): Test > OPTION_MASK_ISA_AVX512VPOPCNTDQ > in x_ix86_isa_flags_explicit rather than x_ix86_isa_flags2_explicit > and set it in x_ix86_isa_flags rather than x_ix86_isa_flags2. > Formatting fixes. > (def_builtin): Treat OPTION_MASK_ISA_AVX512BW or > OPTION_MASK_ISA_AVX512F ored with another option similarly to > OPTION_MASK_ISA_AVX512VL. Even for OPTION_MASK_ISA_AVX512VL > don't > clear it if mask is just OPTION_MASK_ISA_AVX512VL itself. > (ix86_expand_builtin): Don't handle OPTION_MASK_ISA_GFNI and > OPTION_MASK_ISA_VPCLMULQDQ specially, instead handle > OPTION_MASK_ISA_AVX512BW and OPTION_MASK_ISA_AVX512F that > way. > * config/i386/i386-builtin.def: Move AVX512VPOPCNTDQ and > AVX512BITALG > builtins from bdesc_args2 to bdesc_args section. > (__builtin_ia32_compressstoreuqi512_mask, > __builtin_ia32_compressstoreuhi512_mask, > __builtin_ia32_compressstoreuqi256_mask, > __builtin_ia32_expandloadqi512_mask, > __builtin_ia32_expandloadqi512_maskz, > __builtin_ia32_expandloadhi512_mask, > __builtin_ia32_expandloadhi512_maskz, > __builtin_ia32_compressqi512_mask, > __builtin_ia32_compresshi512_mask, > __builtin_ia32_compressqi256_mask, > __builtin_ia32_expandqi512_mask, > __builtin_ia32_expandqi512_maskz, __builtin_ia32_expandhi512_mask, > __builtin_ia32_expandhi512_maskz, __builtin_ia32_expandqi256_mask, > __builtin_ia32_expandqi256_maskz, __builtin_ia32_vpshrd_v32hi_mask, > __builtin_ia32_vpshld_v32hi_mask, > __builtin_ia32_vpshrdv_v32hi_mask, > __builtin_ia32_vpshrdv_v32hi_maskz, > __builtin_ia32_vpshldv_v32hi_mask, > __builtin_ia32_vpshldv_v32hi_maskz, > __builtin_ia32_vpopcountb_v64qi_mask, > __builtin_ia32_vpopcountw_v32hi_mask, > __builtin_ia32_vpshufbitqmb512_mask, > __builtin_ia32_vpshufbitqmb256_mask): Add > " | OPTION_MASK_ISA_AVX512BW". > (__builtin_ia32_expandloadqi256_mask, > __builtin_ia32_expandloadqi256_maskz, > __builtin_ia32_vpopcountb_v32qi_mask): Add > " | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW". > (__builtin_ia32_expandloadhi256_mask, > __builtin_ia32_expandloadhi256_maskz, > __builtin_ia32_expandloadqi128_mask, > __builtin_ia32_expandloadqi128_maskz, > __builtin_ia32_expandloadhi128_mask, > __builtin_ia32_expandloadhi128_maskz, > __builtin_ia32_vpshrd_v16hi, __builtin_ia32_vpshrd_v16hi_mask, > __builtin_ia32_vpshrd_v8hi, __builtin_ia32_vpshrd_v8hi_mask, > __builtin_ia32_vpshrd_v8si, __builtin_ia32_vpshrd_v8si_mask, > __builtin_ia32_vpshrd_v4si, __builtin_ia32_vpshrd_v4si_mask, > __builtin_ia32_vpshrd_v4di, __builtin_ia32_vpshrd_v4di_mask, > __builtin_ia32_vpshrd_v2di, __builtin_ia32_vpshrd_v2di_mask, > __builtin_ia32_vpshld_v16hi, __builtin_ia32_vpshld_v16hi_mask, > __builtin_ia32_vpshld_v8hi, __builtin_ia32_vpshld_v8hi_mask, > __builtin_ia32_vpshld_v8si, __builtin_ia32_vpshld_v8si_mask, > __builtin_ia32_vpshld_v4si, __builtin_ia32_vpshld_v4si_mask, > __builtin_ia32_vpshld_v4di, __builtin_ia32_vpshld_v4di_mask, > __builtin_ia32_vpshld_v2di, __builtin_ia32_vpshld_v2di_mask, > __builtin_ia32_vpshrdv_v16hi, __builtin_ia32_vpshrdv_v16hi_mask, > __builtin_ia32_vpshrdv_v16hi_maskz, __builtin_ia32_vpshrdv_v8hi, > __builtin_ia32_vpshrdv_v8hi_mask, > __builtin_ia32_vpshrdv_v8hi_maskz, > __builtin_ia32_vpshrdv_v8si, __builtin_ia32_vpshrdv_v8si_mask, > __builtin_ia32_vpshrdv_v8si_maskz, __builtin_ia32_vpshrdv_v4si, > __builtin_ia32_vpshrdv_v4si_mask, __builtin_ia32_vpshrdv_v4si_maskz, > __builtin_ia32_vpshrdv_v4di, __builtin_ia32_vpshrdv_v4di_mask, > __builtin_ia32_vpshrdv_v4di_maskz, __builtin_ia32_vpshrdv_v2di, > __builtin_ia32_vpshrdv_v2di_mask, > __builtin_ia32_vpshrdv_v2di_maskz, > __builtin_ia32_vpshldv_v16hi, __builtin_ia32_vpshldv_v16hi_mask, > __builtin_ia32_vpshldv_v16hi_maskz, __builtin_ia32_vpshldv_v8hi, > __builtin_ia32_vpshldv_v8hi_mask, __builtin_ia32_vpshldv_v8hi_maskz, > __builtin_ia32_vpshldv_v8si, __builtin_ia32_vpshldv_v8si_mask, > __builtin_ia32_vpshldv_v8si_maskz, __builtin_ia32_vpshldv_v4si, > __builtin_ia32_vpshldv_v4si_mask, __builtin_ia32_vpshldv_v4si_maskz, > __builtin_ia32_vpshldv_v4di, __builtin_ia32_vpshldv_v4di_mask, > __builtin_ia32_vpshldv_v4di_maskz, __builtin_ia32_vpshldv_v2di, > __builtin_ia32_vpshldv_v2di_mask, __builtin_ia32_vpshldv_v2di_maskz, > __builtin_ia32_vpopcountb_v32qi, __builtin_ia32_vpopcountb_v16qi, > __builtin_ia32_vpopcountb_v16qi_mask, > __builtin_ia32_vpopcountw_v16hi, > __builtin_ia32_vpopcountw_v16hi_mask, > __builtin_ia32_vpopcountw_v8hi, > __builtin_ia32_vpopcountw_v8hi_mask): Add > " | OPTION_MASK_ISA_AVX512VL". > * config/i386/avx512vbmi2intrin.h (_mm512_shrdi_epi16, > _mm512_shrdi_epi32, _mm512_mask_shrdi_epi32, > _mm512_maskz_shrdi_epi32, > _mm512_shrdi_epi64, _mm512_mask_shrdi_epi64, > _mm512_maskz_shrdi_epi64, > _mm512_shldi_epi16, _mm512_shldi_epi32, > _mm512_mask_shldi_epi32, > _mm512_maskz_shldi_epi32, _mm512_shldi_epi64, > _mm512_mask_shldi_epi64, > _mm512_maskz_shldi_epi64, _mm512_shrdv_epi16, > _mm512_shrdv_epi32, > _mm512_mask_shrdv_epi32, _mm512_maskz_shrdv_epi32, > _mm512_shrdv_epi64, > _mm512_mask_shrdv_epi64, _mm512_maskz_shrdv_epi64, > _mm512_shldv_epi16, > _mm512_shldv_epi32, _mm512_mask_shldv_epi32, > _mm512_maskz_shldv_epi32, > _mm512_shldv_epi64, _mm512_mask_shldv_epi64, > _mm512_maskz_shldv_epi64): Don't require avx512bw for these > intrinsics. > * config/i386/avx512bitalgintrin.h (_mm_bitshuffle_epi64_mask, > _mm_mask_bitshuffle_epi64_mask): Likewise. > * common/config/i386/i386-common.c > (OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET, > OPTION_MASK_ISA_AVX512BITALG_SET): Or in > OPTION_MASK_ISA_AVX512F_SET. > (OPTION_MASK_ISA_AVX512F_UNSET): Or in > OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET and > OPTION_MASK_ISA_AVX512BITALG_UNSET. > (OPTION_MASK_ISA2_AVX512F_UNSET, > OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Define. > (ix86_handle_option): For -mno-general-regs-only, clear from > ix86_isa_flags2 OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET > rather than > just OPTION_MASK_ISA_MPX. For -mno-sse{,2,3,4,4.1,4.2,avx,avx2} > and > -mno-ssse3 clear OPTION_MASK_ISA2_AVX512F_UNSET bits from > ix86_isa_flags2. For -mno-avx512f likewise, instead of masking > individually listed ISAs. For -m{,no-}avx512{vpopcntdq,bitalg} adjust > for moving from ix86_isa_flags2 to ix86_isa_flags. > > --- gcc/config/i386/i386.opt.jj 2017-12-22 14:00:04.000000000 +0100 > +++ gcc/config/i386/i386.opt 2017-12-22 14:18:30.113511523 +0100 > @@ -734,7 +734,7 @@ Target Report Mask(ISA_AVX5124VNNIW) Var > Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and > AVX5124VNNIW built-in functions and code generation. > > mavx512vpopcntdq > -Target Report Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags2) Save > +Target Report Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags) Save > Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and > AVX512VPOPCNTDQ built-in functions and code generation. > > mavx512vbmi2 > @@ -746,7 +746,7 @@ Target Report Mask(ISA_AVX512VNNI) Var(i > Support AVX512VNNI built-in functions and code generation. > > mavx512bitalg > -Target Report Mask(ISA_AVX512BITALG) Var(ix86_isa_flags2) Save > +Target Report Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save > Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and > AVX512BITALG built-in functions and code generation. > > mfma > --- gcc/config/i386/i386-c.c.jj 2017-12-22 14:00:04.000000000 +0100 > +++ gcc/config/i386/i386-c.c 2017-12-22 14:22:54.154146866 +0100 > @@ -402,9 +402,9 @@ ix86_target_macros_internal (HOST_WIDE_I > def_or_undef (parse_in, "__SGX__"); > if (isa_flag2 & OPTION_MASK_ISA_AVX5124FMAPS) > def_or_undef (parse_in, "__AVX5124FMAPS__"); > - if (isa_flag2 & OPTION_MASK_ISA_AVX512BITALG) > + if (isa_flag & OPTION_MASK_ISA_AVX512BITALG) > def_or_undef (parse_in, "__AVX512BITALG__"); > - if (isa_flag2 & OPTION_MASK_ISA_AVX512VPOPCNTDQ) > + if (isa_flag & OPTION_MASK_ISA_AVX512VPOPCNTDQ) > def_or_undef (parse_in, "__AVX512VPOPCNTDQ__"); > if (isa_flag & OPTION_MASK_ISA_FMA) > def_or_undef (parse_in, "__FMA__"); > --- gcc/config/i386/i386.c.jj 2017-12-22 14:00:04.000000000 +0100 > +++ gcc/config/i386/i386.c 2017-12-22 15:52:29.345353491 +0100 > @@ -2758,16 +2758,16 @@ ix86_target_string (HOST_WIDE_INT isa, H > { "-msgx", OPTION_MASK_ISA_SGX }, > { "-mavx5124vnniw", OPTION_MASK_ISA_AVX5124VNNIW }, > { "-mavx5124fmaps", OPTION_MASK_ISA_AVX5124FMAPS }, > - { "-mavx512vpopcntdq", OPTION_MASK_ISA_AVX512VPOPCNTDQ }, > { "-mibt", OPTION_MASK_ISA_IBT }, > { "-mhle", OPTION_MASK_ISA_HLE }, > { "-mmovbe", OPTION_MASK_ISA_MOVBE }, > { "-mclzero", OPTION_MASK_ISA_CLZERO }, > - { "-mmwaitx", OPTION_MASK_ISA_MWAITX }, > - { "-mavx512bitalg", OPTION_MASK_ISA_AVX512BITALG } > + { "-mmwaitx", OPTION_MASK_ISA_MWAITX } > }; > static struct ix86_target_opts isa_opts[] = > { > + { "-mavx512vpopcntdq", OPTION_MASK_ISA_AVX512VPOPCNTDQ }, > + { "-mavx512bitalg", OPTION_MASK_ISA_AVX512BITALG }, > { "-mvpclmulqdq", OPTION_MASK_ISA_VPCLMULQDQ }, > { "-mgfni", OPTION_MASK_ISA_GFNI }, > { "-mavx512vnni", OPTION_MASK_ISA_AVX512VNNI }, > @@ -4104,14 +4104,17 @@ ix86_option_override_internal (bool main > opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA; > > if (processor_alias_table[i].flags & PTA_AVX5124VNNIW > - && !(opts->x_ix86_isa_flags2_explicit & > OPTION_MASK_ISA_AVX5124VNNIW)) > + && !(opts->x_ix86_isa_flags2_explicit > + & OPTION_MASK_ISA_AVX5124VNNIW)) > opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW; > if (processor_alias_table[i].flags & PTA_AVX5124FMAPS > - && !(opts->x_ix86_isa_flags2_explicit & > OPTION_MASK_ISA_AVX5124FMAPS)) > + && !(opts->x_ix86_isa_flags2_explicit > + & OPTION_MASK_ISA_AVX5124FMAPS)) > opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS; > if (processor_alias_table[i].flags & PTA_AVX512VPOPCNTDQ > - && !(opts->x_ix86_isa_flags2_explicit & > OPTION_MASK_ISA_AVX512VPOPCNTDQ)) > - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ; > + && !(opts->x_ix86_isa_flags_explicit > + & OPTION_MASK_ISA_AVX512VPOPCNTDQ)) > + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ; > if (processor_alias_table[i].flags & PTA_SGX > && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX)) > opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX; > @@ -29795,13 +29798,21 @@ def_builtin (HOST_WIDE_INT mask, const c > { > ix86_builtins_isa[(int) code].isa = mask; > > - /* OPTION_MASK_ISA_AVX512VL has special meaning. Despite of generic > case, > - where any bit set means that built-in is enable, this bit must be *and- > ed* > - with another one. E.g.: OPTION_MASK_ISA_AVX512DQ | > OPTION_MASK_ISA_AVX512VL > - means that *both* cpuid bits must be set for the built-in to be > available. > - Handle this here. */ > - if (mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL) > + /* OPTION_MASK_ISA_AVX512{F,VL,BW} have special meaning. Despite of > + generic case, where any bit set means that built-in is enable, this > + bit must be *and-ed* with another one. E.g.: > + OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL > + means that *both* cpuid bits must be set for the built-in to > + be available. Handle this here. */ > + if ((mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL) > + && mask != OPTION_MASK_ISA_AVX512VL) > mask &= ~OPTION_MASK_ISA_AVX512VL; > + if ((mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512BW) > + && mask != OPTION_MASK_ISA_AVX512BW) > + mask &= ~OPTION_MASK_ISA_AVX512BW; > + if ((mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512F) > + && mask != OPTION_MASK_ISA_AVX512F) > + mask &= ~OPTION_MASK_ISA_AVX512F; > > mask &= ~OPTION_MASK_ISA_64BIT; > if (mask == 0 > @@ -35364,25 +35375,28 @@ ix86_expand_builtin (tree exp, rtx targe > Originally the builtin was not created if it wasn't applicable to the > current ISA based on the command line switches. With function specific > options, we need to check in the context of the function making the call > - whether it is supported. Treat AVX512VL and MMX specially. For other > flags, > - if isa includes more than one ISA bit, treat those are requiring any > - of them. For AVX512VL, require both AVX512VL and the non-AVX512VL > - ISAs. Likewise for MMX, require both MMX and the non-MMX ISAs. > + whether it is supported. Treat AVX512{VL,BW,F} and MMX specially. For > + other flags, if isa includes more than one ISA bit, treat those are > + requiring any of them. For AVX512VL, require both AVX512VL and the > + non-AVX512VL ISAs. Likewise for MMX, require both MMX and the non- > MMX > + ISAs. Similarly for AVX512F and AVX512BW. > Similarly for 64BIT, but we shouldn't be building such builtins > at all, -m64 is a whole TU option. */ > if (((ix86_builtins_isa[fcode].isa > & ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_MMX > - | OPTION_MASK_ISA_64BIT | OPTION_MASK_ISA_GFNI > - | OPTION_MASK_ISA_VPCLMULQDQ)) > + | OPTION_MASK_ISA_64BIT | OPTION_MASK_ISA_AVX512BW > + | OPTION_MASK_ISA_AVX512F)) > && !(ix86_builtins_isa[fcode].isa > & ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_MMX > - | OPTION_MASK_ISA_64BIT | OPTION_MASK_ISA_GFNI > - | OPTION_MASK_ISA_VPCLMULQDQ) > + | OPTION_MASK_ISA_64BIT | OPTION_MASK_ISA_AVX512BW > + | OPTION_MASK_ISA_AVX512F) > & ix86_isa_flags)) > || ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_AVX512VL) > && !(ix86_isa_flags & OPTION_MASK_ISA_AVX512VL)) > - || ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_GFNI) > - && !(ix86_isa_flags & OPTION_MASK_ISA_GFNI)) > + || ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_AVX512BW) > + && !(ix86_isa_flags & OPTION_MASK_ISA_AVX512BW)) > + || ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_AVX512F) > + && !(ix86_isa_flags & OPTION_MASK_ISA_AVX512F)) > || ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_MMX) > && !(ix86_isa_flags & OPTION_MASK_ISA_MMX)) > || (ix86_builtins_isa[fcode].isa2 > --- gcc/config/i386/i386-builtin.def.jj 2017-12-22 14:03:05.000000000 > +0100 > +++ gcc/config/i386/i386-builtin.def 2017-12-22 18:00:12.579239678 +0100 > @@ -393,27 +393,27 @@ BDESC (OPTION_MASK_ISA_PKU, CODE_FOR_rdp > BDESC (OPTION_MASK_ISA_PKU, CODE_FOR_wrpkru, "__builtin_ia32_wrpkru", > IX86_BUILTIN_WRPKRU, UNKNOWN, (int) VOID_FTYPE_UNSIGNED) > > /* VBMI2 */ > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, > CODE_FOR_compressstorev64qi_mask, > "__builtin_ia32_compressstoreuqi512_mask", > IX86_BUILTIN_PCOMPRESSBSTORE512, UNKNOWN, (int) > VOID_FTYPE_PV64QI_V64QI_UDI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, > CODE_FOR_compressstorev32hi_mask, > "__builtin_ia32_compressstoreuhi512_mask", > IX86_BUILTIN_PCOMPRESSWSTORE512, UNKNOWN, (int) > VOID_FTYPE_PV32HI_V32HI_USI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_compressstorev32qi_mask, > "__builtin_ia32_compressstoreuqi256_mask", > IX86_BUILTIN_PCOMPRESSBSTORE256, UNKNOWN, (int) > VOID_FTYPE_PV32QI_V32QI_USI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_compressstorev64qi_mask, > "__builtin_ia32_compressstoreuqi512_mask", > IX86_BUILTIN_PCOMPRESSBSTORE512, UNKNOWN, (int) > VOID_FTYPE_PV64QI_V64QI_UDI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_compressstorev32hi_mask, > "__builtin_ia32_compressstoreuhi512_mask", > IX86_BUILTIN_PCOMPRESSWSTORE512, UNKNOWN, (int) > VOID_FTYPE_PV32HI_V32HI_USI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL | > OPTION_MASK_ISA_AVX512BW, CODE_FOR_compressstorev32qi_mask, > "__builtin_ia32_compressstoreuqi256_mask", > IX86_BUILTIN_PCOMPRESSBSTORE256, UNKNOWN, (int) > VOID_FTYPE_PV32QI_V32QI_USI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_compressstorev16qi_mask, > "__builtin_ia32_compressstoreuqi128_mask", > IX86_BUILTIN_PCOMPRESSBSTORE128, UNKNOWN, (int) > VOID_FTYPE_PV16QI_V16QI_UHI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_compressstorev16hi_mask, > "__builtin_ia32_compressstoreuhi256_mask", > IX86_BUILTIN_PCOMPRESSWSTORE256, UNKNOWN, (int) > VOID_FTYPE_PV16HI_V16HI_UHI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_compressstorev8hi_mask, > "__builtin_ia32_compressstoreuhi128_mask", > IX86_BUILTIN_PCOMPRESSWSTORE128, UNKNOWN, (int) > VOID_FTYPE_PV8HI_V8HI_UQI) > > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv64qi_mask, > "__builtin_ia32_expandloadqi512_mask", IX86_BUILTIN_PEXPANDBLOAD512, > UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_UDI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv64qi_maskz, > "__builtin_ia32_expandloadqi512_maskz", IX86_BUILTIN_PEXPANDBLOAD512Z, > UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_UDI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv32hi_mask, > "__builtin_ia32_expandloadhi512_mask", IX86_BUILTIN_PEXPANDWLOAD512, > UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_USI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv32hi_maskz, > "__builtin_ia32_expandloadhi512_maskz", > IX86_BUILTIN_PEXPANDWLOAD512Z, UNKNOWN, (int) > V32HI_FTYPE_PCV32HI_V32HI_USI) > - > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv32qi_mask, > "__builtin_ia32_expandloadqi256_mask", IX86_BUILTIN_PEXPANDBLOAD256, > UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_USI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv32qi_maskz, > "__builtin_ia32_expandloadqi256_maskz", IX86_BUILTIN_PEXPANDBLOAD256Z, > UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_USI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv16hi_mask, > "__builtin_ia32_expandloadhi256_mask", IX86_BUILTIN_PEXPANDWLOAD256, > UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_UHI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv16hi_maskz, > "__builtin_ia32_expandloadhi256_maskz", > IX86_BUILTIN_PEXPANDWLOAD256Z, UNKNOWN, (int) > V16HI_FTYPE_PCV16HI_V16HI_UHI) > - > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv16qi_mask, > "__builtin_ia32_expandloadqi128_mask", IX86_BUILTIN_PEXPANDBLOAD128, > UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_UHI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv16qi_maskz, > "__builtin_ia32_expandloadqi128_maskz", IX86_BUILTIN_PEXPANDBLOAD128Z, > UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_UHI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv8hi_mask, > "__builtin_ia32_expandloadhi128_mask", IX86_BUILTIN_PEXPANDWLOAD128, > UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_UQI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv8hi_maskz, > "__builtin_ia32_expandloadhi128_maskz", > IX86_BUILTIN_PEXPANDWLOAD128Z, UNKNOWN, (int) > V8HI_FTYPE_PCV8HI_V8HI_UQI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_expandv64qi_mask, "__builtin_ia32_expandloadqi512_mask", > IX86_BUILTIN_PEXPANDBLOAD512, UNKNOWN, (int) > V64QI_FTYPE_PCV64QI_V64QI_UDI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_expandv64qi_maskz, "__builtin_ia32_expandloadqi512_maskz", > IX86_BUILTIN_PEXPANDBLOAD512Z, UNKNOWN, (int) > V64QI_FTYPE_PCV64QI_V64QI_UDI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_expandv32hi_mask, "__builtin_ia32_expandloadhi512_mask", > IX86_BUILTIN_PEXPANDWLOAD512, UNKNOWN, (int) > V32HI_FTYPE_PCV32HI_V32HI_USI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_expandv32hi_maskz, "__builtin_ia32_expandloadhi512_maskz", > IX86_BUILTIN_PEXPANDWLOAD512Z, UNKNOWN, (int) > V32HI_FTYPE_PCV32HI_V32HI_USI) > + > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL | > OPTION_MASK_ISA_AVX512BW, CODE_FOR_expandv32qi_mask, > "__builtin_ia32_expandloadqi256_mask", IX86_BUILTIN_PEXPANDBLOAD256, > UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_USI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL | > OPTION_MASK_ISA_AVX512BW, CODE_FOR_expandv32qi_maskz, > "__builtin_ia32_expandloadqi256_maskz", IX86_BUILTIN_PEXPANDBLOAD256Z, > UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_USI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_expandv16hi_mask, "__builtin_ia32_expandloadhi256_mask", > IX86_BUILTIN_PEXPANDWLOAD256, UNKNOWN, (int) > V16HI_FTYPE_PCV16HI_V16HI_UHI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_expandv16hi_maskz, "__builtin_ia32_expandloadhi256_maskz", > IX86_BUILTIN_PEXPANDWLOAD256Z, UNKNOWN, (int) > V16HI_FTYPE_PCV16HI_V16HI_UHI) > + > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_expandv16qi_mask, "__builtin_ia32_expandloadqi128_mask", > IX86_BUILTIN_PEXPANDBLOAD128, UNKNOWN, (int) > V16QI_FTYPE_PCV16QI_V16QI_UHI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_expandv16qi_maskz, "__builtin_ia32_expandloadqi128_maskz", > IX86_BUILTIN_PEXPANDBLOAD128Z, UNKNOWN, (int) > V16QI_FTYPE_PCV16QI_V16QI_UHI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_expandv8hi_mask, "__builtin_ia32_expandloadhi128_mask", > IX86_BUILTIN_PEXPANDWLOAD128, UNKNOWN, (int) > V8HI_FTYPE_PCV8HI_V8HI_UQI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_expandv8hi_maskz, "__builtin_ia32_expandloadhi128_maskz", > IX86_BUILTIN_PEXPANDWLOAD128Z, UNKNOWN, (int) > V8HI_FTYPE_PCV8HI_V8HI_UQI) > > BDESC_END (SPECIAL_ARGS, ARGS) > > @@ -2418,18 +2418,18 @@ BDESC (OPTION_MASK_ISA_AVX512VBMI | OPTI > BDESC (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_avx512vl_vpermi2varv16qi3_mask, > "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, > UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI) > > /* VBMI2 */ > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_compressv64qi_mask, > "__builtin_ia32_compressqi512_mask", IX86_BUILTIN_PCOMPRESSB512, > UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_compressv32hi_mask, > "__builtin_ia32_compresshi512_mask", IX86_BUILTIN_PCOMPRESSW512, > UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_USI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_compressv32qi_mask, "__builtin_ia32_compressqi256_mask", > IX86_BUILTIN_PCOMPRESSB256, UNKNOWN, (int) > V32QI_FTYPE_V32QI_V32QI_USI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_compressv64qi_mask, "__builtin_ia32_compressqi512_mask", > IX86_BUILTIN_PCOMPRESSB512, UNKNOWN, (int) > V64QI_FTYPE_V64QI_V64QI_UDI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_compressv32hi_mask, "__builtin_ia32_compresshi512_mask", > IX86_BUILTIN_PCOMPRESSW512, UNKNOWN, (int) > V32HI_FTYPE_V32HI_V32HI_USI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL | > OPTION_MASK_ISA_AVX512BW, CODE_FOR_compressv32qi_mask, > "__builtin_ia32_compressqi256_mask", IX86_BUILTIN_PCOMPRESSB256, > UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_compressv16qi_mask, "__builtin_ia32_compressqi128_mask", > IX86_BUILTIN_PCOMPRESSB128, UNKNOWN, (int) > V16QI_FTYPE_V16QI_V16QI_UHI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_compressv16hi_mask, "__builtin_ia32_compresshi256_mask", > IX86_BUILTIN_PCOMPRESSW256, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_UHI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_compressv8hi_mask, "__builtin_ia32_compresshi128_mask", > IX86_BUILTIN_PCOMPRESSW128, UNKNOWN, (int) > V8HI_FTYPE_V8HI_V8HI_UQI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv64qi_mask, > "__builtin_ia32_expandqi512_mask", IX86_BUILTIN_PEXPANDB512, > UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv64qi_maskz, > "__builtin_ia32_expandqi512_maskz", IX86_BUILTIN_PEXPANDB512Z, > UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv32hi_mask, > "__builtin_ia32_expandhi512_mask", IX86_BUILTIN_PEXPANDW512, > UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_USI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_expandv32hi_maskz, > "__builtin_ia32_expandhi512_maskz", IX86_BUILTIN_PEXPANDW512Z, > UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_USI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_expandv32qi_mask, "__builtin_ia32_expandqi256_mask", > IX86_BUILTIN_PEXPANDB256, UNKNOWN, (int) > V32QI_FTYPE_V32QI_V32QI_USI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_expandv32qi_maskz, "__builtin_ia32_expandqi256_maskz", > IX86_BUILTIN_PEXPANDB256Z, UNKNOWN, (int) > V32QI_FTYPE_V32QI_V32QI_USI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_expandv64qi_mask, "__builtin_ia32_expandqi512_mask", > IX86_BUILTIN_PEXPANDB512, UNKNOWN, (int) > V64QI_FTYPE_V64QI_V64QI_UDI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_expandv64qi_maskz, "__builtin_ia32_expandqi512_maskz", > IX86_BUILTIN_PEXPANDB512Z, UNKNOWN, (int) > V64QI_FTYPE_V64QI_V64QI_UDI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_expandv32hi_mask, "__builtin_ia32_expandhi512_mask", > IX86_BUILTIN_PEXPANDW512, UNKNOWN, (int) > V32HI_FTYPE_V32HI_V32HI_USI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_expandv32hi_maskz, "__builtin_ia32_expandhi512_maskz", > IX86_BUILTIN_PEXPANDW512Z, UNKNOWN, (int) > V32HI_FTYPE_V32HI_V32HI_USI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL | > OPTION_MASK_ISA_AVX512BW, CODE_FOR_expandv32qi_mask, > "__builtin_ia32_expandqi256_mask", IX86_BUILTIN_PEXPANDB256, > UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL | > OPTION_MASK_ISA_AVX512BW, CODE_FOR_expandv32qi_maskz, > "__builtin_ia32_expandqi256_maskz", IX86_BUILTIN_PEXPANDB256Z, > UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_expandv16qi_mask, "__builtin_ia32_expandqi128_mask", > IX86_BUILTIN_PEXPANDB128, UNKNOWN, (int) > V16QI_FTYPE_V16QI_V16QI_UHI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_expandv16qi_maskz, "__builtin_ia32_expandqi128_maskz", > IX86_BUILTIN_PEXPANDB128Z, UNKNOWN, (int) > V16QI_FTYPE_V16QI_V16QI_UHI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_expandv16hi_mask, "__builtin_ia32_expandhi256_mask", > IX86_BUILTIN_PEXPANDW256, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_UHI) > @@ -2437,97 +2437,97 @@ BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPT > BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_expandv8hi_mask, "__builtin_ia32_expandhi128_mask", > IX86_BUILTIN_PEXPANDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_expandv8hi_maskz, "__builtin_ia32_expandhi128_maskz", > IX86_BUILTIN_PEXPANDW128Z, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v32hi, > "__builtin_ia32_vpshrd_v32hi", IX86_BUILTIN_VPSHRDV32HI, UNKNOWN, (int) > V32HI_FTYPE_V32HI_V32HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v32hi_mask, > "__builtin_ia32_vpshrd_v32hi_mask", IX86_BUILTIN_VPSHRDV32HI_MASK, > UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_INT_V32HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v16hi, > "__builtin_ia32_vpshrd_v16hi", IX86_BUILTIN_VPSHRDV16HI, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v16hi_mask, > "__builtin_ia32_vpshrd_v16hi_mask", IX86_BUILTIN_VPSHRDV16HI_MASK, > UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT_V16HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v8hi, > "__builtin_ia32_vpshrd_v8hi", IX86_BUILTIN_VPSHRDV8HI, UNKNOWN, (int) > V8HI_FTYPE_V8HI_V8HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v8hi_mask, > "__builtin_ia32_vpshrd_v8hi_mask", IX86_BUILTIN_VPSHRDV8HI_MASK, > UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT_V8HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_vpshrd_v32hi_mask, "__builtin_ia32_vpshrd_v32hi_mask", > IX86_BUILTIN_VPSHRDV32HI_MASK, UNKNOWN, (int) > V32HI_FTYPE_V32HI_V32HI_INT_V32HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrd_v16hi, "__builtin_ia32_vpshrd_v16hi", > IX86_BUILTIN_VPSHRDV16HI, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrd_v16hi_mask, "__builtin_ia32_vpshrd_v16hi_mask", > IX86_BUILTIN_VPSHRDV16HI_MASK, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_INT_V16HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrd_v8hi, "__builtin_ia32_vpshrd_v8hi", > IX86_BUILTIN_VPSHRDV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrd_v8hi_mask, "__builtin_ia32_vpshrd_v8hi_mask", > IX86_BUILTIN_VPSHRDV8HI_MASK, UNKNOWN, (int) > V8HI_FTYPE_V8HI_V8HI_INT_V8HI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v16si, > "__builtin_ia32_vpshrd_v16si", IX86_BUILTIN_VPSHRDV16SI, UNKNOWN, (int) > V16SI_FTYPE_V16SI_V16SI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v16si_mask, > "__builtin_ia32_vpshrd_v16si_mask", IX86_BUILTIN_VPSHRDV16SI_MASK, > UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v8si, > "__builtin_ia32_vpshrd_v8si", IX86_BUILTIN_VPSHRDV8SI, UNKNOWN, (int) > V8SI_FTYPE_V8SI_V8SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v8si_mask, > "__builtin_ia32_vpshrd_v8si_mask", IX86_BUILTIN_VPSHRDV8SI_MASK, > UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v4si, > "__builtin_ia32_vpshrd_v4si", IX86_BUILTIN_VPSHRDV4SI, UNKNOWN, (int) > V4SI_FTYPE_V4SI_V4SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v4si_mask, > "__builtin_ia32_vpshrd_v4si_mask", IX86_BUILTIN_VPSHRDV4SI_MASK, > UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrd_v8si, "__builtin_ia32_vpshrd_v8si", > IX86_BUILTIN_VPSHRDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrd_v8si_mask, "__builtin_ia32_vpshrd_v8si_mask", > IX86_BUILTIN_VPSHRDV8SI_MASK, UNKNOWN, (int) > V8SI_FTYPE_V8SI_V8SI_INT_V8SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrd_v4si, "__builtin_ia32_vpshrd_v4si", > IX86_BUILTIN_VPSHRDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrd_v4si_mask, "__builtin_ia32_vpshrd_v4si_mask", > IX86_BUILTIN_VPSHRDV4SI_MASK, UNKNOWN, (int) > V4SI_FTYPE_V4SI_V4SI_INT_V4SI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v8di, > "__builtin_ia32_vpshrd_v8di", IX86_BUILTIN_VPSHRDV8DI, UNKNOWN, (int) > V8DI_FTYPE_V8DI_V8DI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v8di_mask, > "__builtin_ia32_vpshrd_v8di_mask", IX86_BUILTIN_VPSHRDV8DI_MASK, > UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v4di, > "__builtin_ia32_vpshrd_v4di", IX86_BUILTIN_VPSHRDV4DI, UNKNOWN, (int) > V4DI_FTYPE_V4DI_V4DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v4di_mask, > "__builtin_ia32_vpshrd_v4di_mask", IX86_BUILTIN_VPSHRDV4DI_MASK, > UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v2di, > "__builtin_ia32_vpshrd_v2di", IX86_BUILTIN_VPSHRDV2DI, UNKNOWN, (int) > V2DI_FTYPE_V2DI_V2DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrd_v2di_mask, > "__builtin_ia32_vpshrd_v2di_mask", IX86_BUILTIN_VPSHRDV2DI_MASK, > UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrd_v4di, "__builtin_ia32_vpshrd_v4di", > IX86_BUILTIN_VPSHRDV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrd_v4di_mask, "__builtin_ia32_vpshrd_v4di_mask", > IX86_BUILTIN_VPSHRDV4DI_MASK, UNKNOWN, (int) > V4DI_FTYPE_V4DI_V4DI_INT_V4DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrd_v2di, "__builtin_ia32_vpshrd_v2di", > IX86_BUILTIN_VPSHRDV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrd_v2di_mask, "__builtin_ia32_vpshrd_v2di_mask", > IX86_BUILTIN_VPSHRDV2DI_MASK, UNKNOWN, (int) > V2DI_FTYPE_V2DI_V2DI_INT_V2DI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v32hi, > "__builtin_ia32_vpshld_v32hi", IX86_BUILTIN_VPSHLDV32HI, UNKNOWN, (int) > V32HI_FTYPE_V32HI_V32HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v32hi_mask, > "__builtin_ia32_vpshld_v32hi_mask", IX86_BUILTIN_VPSHLDV32HI_MASK, > UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_INT_V32HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v16hi, > "__builtin_ia32_vpshld_v16hi", IX86_BUILTIN_VPSHLDV16HI, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v16hi_mask, > "__builtin_ia32_vpshld_v16hi_mask", IX86_BUILTIN_VPSHLDV16HI_MASK, > UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT_V16HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v8hi, > "__builtin_ia32_vpshld_v8hi", IX86_BUILTIN_VPSHLDV8HI, UNKNOWN, (int) > V8HI_FTYPE_V8HI_V8HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v8hi_mask, > "__builtin_ia32_vpshld_v8hi_mask", IX86_BUILTIN_VPSHLDV8HI_MASK, > UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT_V8HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_vpshld_v32hi_mask, "__builtin_ia32_vpshld_v32hi_mask", > IX86_BUILTIN_VPSHLDV32HI_MASK, UNKNOWN, (int) > V32HI_FTYPE_V32HI_V32HI_INT_V32HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshld_v16hi, "__builtin_ia32_vpshld_v16hi", > IX86_BUILTIN_VPSHLDV16HI, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshld_v16hi_mask, "__builtin_ia32_vpshld_v16hi_mask", > IX86_BUILTIN_VPSHLDV16HI_MASK, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_INT_V16HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshld_v8hi, "__builtin_ia32_vpshld_v8hi", > IX86_BUILTIN_VPSHLDV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshld_v8hi_mask, "__builtin_ia32_vpshld_v8hi_mask", > IX86_BUILTIN_VPSHLDV8HI_MASK, UNKNOWN, (int) > V8HI_FTYPE_V8HI_V8HI_INT_V8HI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v16si, > "__builtin_ia32_vpshld_v16si", IX86_BUILTIN_VPSHLDV16SI, UNKNOWN, (int) > V16SI_FTYPE_V16SI_V16SI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v16si_mask, > "__builtin_ia32_vpshld_v16si_mask", IX86_BUILTIN_VPSHLDV16SI_MASK, > UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v8si, > "__builtin_ia32_vpshld_v8si", IX86_BUILTIN_VPSHLDV8SI, UNKNOWN, (int) > V8SI_FTYPE_V8SI_V8SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v8si_mask, > "__builtin_ia32_vpshld_v8si_mask", IX86_BUILTIN_VPSHLDV8SI_MASK, > UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v4si, > "__builtin_ia32_vpshld_v4si", IX86_BUILTIN_VPSHLDV4SI, UNKNOWN, (int) > V4SI_FTYPE_V4SI_V4SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v4si_mask, > "__builtin_ia32_vpshld_v4si_mask", IX86_BUILTIN_VPSHLDV4SI_MASK, > UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshld_v8si, "__builtin_ia32_vpshld_v8si", > IX86_BUILTIN_VPSHLDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshld_v8si_mask, "__builtin_ia32_vpshld_v8si_mask", > IX86_BUILTIN_VPSHLDV8SI_MASK, UNKNOWN, (int) > V8SI_FTYPE_V8SI_V8SI_INT_V8SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshld_v4si, "__builtin_ia32_vpshld_v4si", > IX86_BUILTIN_VPSHLDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshld_v4si_mask, "__builtin_ia32_vpshld_v4si_mask", > IX86_BUILTIN_VPSHLDV4SI_MASK, UNKNOWN, (int) > V4SI_FTYPE_V4SI_V4SI_INT_V4SI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v8di, > "__builtin_ia32_vpshld_v8di", IX86_BUILTIN_VPSHLDV8DI, UNKNOWN, (int) > V8DI_FTYPE_V8DI_V8DI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v8di_mask, > "__builtin_ia32_vpshld_v8di_mask", IX86_BUILTIN_VPSHLDV8DI_MASK, > UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v4di, > "__builtin_ia32_vpshld_v4di", IX86_BUILTIN_VPSHLDV4DI, UNKNOWN, (int) > V4DI_FTYPE_V4DI_V4DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v4di_mask, > "__builtin_ia32_vpshld_v4di_mask", IX86_BUILTIN_VPSHLDV4DI_MASK, > UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v2di, > "__builtin_ia32_vpshld_v2di", IX86_BUILTIN_VPSHLDV2DI, UNKNOWN, (int) > V2DI_FTYPE_V2DI_V2DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v2di_mask, > "__builtin_ia32_vpshld_v2di_mask", IX86_BUILTIN_VPSHLDV2DI_MASK, > UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshld_v4di, "__builtin_ia32_vpshld_v4di", > IX86_BUILTIN_VPSHLDV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshld_v4di_mask, "__builtin_ia32_vpshld_v4di_mask", > IX86_BUILTIN_VPSHLDV4DI_MASK, UNKNOWN, (int) > V4DI_FTYPE_V4DI_V4DI_INT_V4DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshld_v2di, "__builtin_ia32_vpshld_v2di", > IX86_BUILTIN_VPSHLDV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshld_v2di_mask, "__builtin_ia32_vpshld_v2di_mask", > IX86_BUILTIN_VPSHLDV2DI_MASK, UNKNOWN, (int) > V2DI_FTYPE_V2DI_V2DI_INT_V2DI_INT) > > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v32hi, > "__builtin_ia32_vpshrdv_v32hi", IX86_BUILTIN_VPSHRDVV32HI, UNKNOWN, > (int) V32HI_FTYPE_V32HI_V32HI_V32HI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v32hi_mask, > "__builtin_ia32_vpshrdv_v32hi_mask", IX86_BUILTIN_VPSHRDVV32HI_MASK, > UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v32hi_maskz, > "__builtin_ia32_vpshrdv_v32hi_maskz", IX86_BUILTIN_VPSHRDVV32HI_MASKZ, > UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v16hi, > "__builtin_ia32_vpshrdv_v16hi", IX86_BUILTIN_VPSHRDVV16HI, UNKNOWN, > (int) V16HI_FTYPE_V16HI_V16HI_V16HI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v16hi_mask, > "__builtin_ia32_vpshrdv_v16hi_mask", IX86_BUILTIN_VPSHRDVV16HI_MASK, > UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v16hi_maskz, > "__builtin_ia32_vpshrdv_v16hi_maskz", IX86_BUILTIN_VPSHRDVV16HI_MASKZ, > UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8hi, > "__builtin_ia32_vpshrdv_v8hi", IX86_BUILTIN_VPSHRDVV8HI, UNKNOWN, (int) > V8HI_FTYPE_V8HI_V8HI_V8HI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8hi_mask, > "__builtin_ia32_vpshrdv_v8hi_mask", IX86_BUILTIN_VPSHRDVV8HI_MASK, > UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8hi_maskz, > "__builtin_ia32_vpshrdv_v8hi_maskz", IX86_BUILTIN_VPSHRDVV8HI_MASKZ, > UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_vpshrdv_v32hi_mask, "__builtin_ia32_vpshrdv_v32hi_mask", > IX86_BUILTIN_VPSHRDVV32HI_MASK, UNKNOWN, (int) > V32HI_FTYPE_V32HI_V32HI_V32HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_vpshrdv_v32hi_maskz, "__builtin_ia32_vpshrdv_v32hi_maskz", > IX86_BUILTIN_VPSHRDVV32HI_MASKZ, UNKNOWN, (int) > V32HI_FTYPE_V32HI_V32HI_V32HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v16hi, "__builtin_ia32_vpshrdv_v16hi", > IX86_BUILTIN_VPSHRDVV16HI, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_V16HI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v16hi_mask, "__builtin_ia32_vpshrdv_v16hi_mask", > IX86_BUILTIN_VPSHRDVV16HI_MASK, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_V16HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v16hi_maskz, "__builtin_ia32_vpshrdv_v16hi_maskz", > IX86_BUILTIN_VPSHRDVV16HI_MASKZ, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_V16HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v8hi, "__builtin_ia32_vpshrdv_v8hi", > IX86_BUILTIN_VPSHRDVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v8hi_mask, "__builtin_ia32_vpshrdv_v8hi_mask", > IX86_BUILTIN_VPSHRDVV8HI_MASK, UNKNOWN, (int) > V8HI_FTYPE_V8HI_V8HI_V8HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v8hi_maskz, "__builtin_ia32_vpshrdv_v8hi_maskz", > IX86_BUILTIN_VPSHRDVV8HI_MASKZ, UNKNOWN, (int) > V8HI_FTYPE_V8HI_V8HI_V8HI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v16si, > "__builtin_ia32_vpshrdv_v16si", IX86_BUILTIN_VPSHRDVV16SI, UNKNOWN, > (int) V16SI_FTYPE_V16SI_V16SI_V16SI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v16si_mask, > "__builtin_ia32_vpshrdv_v16si_mask", IX86_BUILTIN_VPSHRDVV16SI_MASK, > UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v16si_maskz, > "__builtin_ia32_vpshrdv_v16si_maskz", IX86_BUILTIN_VPSHRDVV16SI_MASKZ, > UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8si, > "__builtin_ia32_vpshrdv_v8si", IX86_BUILTIN_VPSHRDVV8SI, UNKNOWN, (int) > V8SI_FTYPE_V8SI_V8SI_V8SI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8si_mask, > "__builtin_ia32_vpshrdv_v8si_mask", IX86_BUILTIN_VPSHRDVV8SI_MASK, > UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8si_maskz, > "__builtin_ia32_vpshrdv_v8si_maskz", IX86_BUILTIN_VPSHRDVV8SI_MASKZ, > UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v4si, > "__builtin_ia32_vpshrdv_v4si", IX86_BUILTIN_VPSHRDVV4SI, UNKNOWN, (int) > V4SI_FTYPE_V4SI_V4SI_V4SI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v4si_mask, > "__builtin_ia32_vpshrdv_v4si_mask", IX86_BUILTIN_VPSHRDVV4SI_MASK, > UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v4si_maskz, > "__builtin_ia32_vpshrdv_v4si_maskz", IX86_BUILTIN_VPSHRDVV4SI_MASKZ, > UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v8si, "__builtin_ia32_vpshrdv_v8si", > IX86_BUILTIN_VPSHRDVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v8si_mask, "__builtin_ia32_vpshrdv_v8si_mask", > IX86_BUILTIN_VPSHRDVV8SI_MASK, UNKNOWN, (int) > V8SI_FTYPE_V8SI_V8SI_V8SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v8si_maskz, "__builtin_ia32_vpshrdv_v8si_maskz", > IX86_BUILTIN_VPSHRDVV8SI_MASKZ, UNKNOWN, (int) > V8SI_FTYPE_V8SI_V8SI_V8SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v4si, "__builtin_ia32_vpshrdv_v4si", > IX86_BUILTIN_VPSHRDVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v4si_mask, "__builtin_ia32_vpshrdv_v4si_mask", > IX86_BUILTIN_VPSHRDVV4SI_MASK, UNKNOWN, (int) > V4SI_FTYPE_V4SI_V4SI_V4SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v4si_maskz, "__builtin_ia32_vpshrdv_v4si_maskz", > IX86_BUILTIN_VPSHRDVV4SI_MASKZ, UNKNOWN, (int) > V4SI_FTYPE_V4SI_V4SI_V4SI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8di, > "__builtin_ia32_vpshrdv_v8di", IX86_BUILTIN_VPSHRDVV8DI, UNKNOWN, (int) > V8DI_FTYPE_V8DI_V8DI_V8DI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8di_mask, > "__builtin_ia32_vpshrdv_v8di_mask", IX86_BUILTIN_VPSHRDVV8DI_MASK, > UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8di_maskz, > "__builtin_ia32_vpshrdv_v8di_maskz", IX86_BUILTIN_VPSHRDVV8DI_MASKZ, > UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v4di, > "__builtin_ia32_vpshrdv_v4di", IX86_BUILTIN_VPSHRDVV4DI, UNKNOWN, (int) > V4DI_FTYPE_V4DI_V4DI_V4DI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v4di_mask, > "__builtin_ia32_vpshrdv_v4di_mask", IX86_BUILTIN_VPSHRDVV4DI_MASK, > UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v4di_maskz, > "__builtin_ia32_vpshrdv_v4di_maskz", IX86_BUILTIN_VPSHRDVV4DI_MASKZ, > UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v2di, > "__builtin_ia32_vpshrdv_v2di", IX86_BUILTIN_VPSHRDVV2DI, UNKNOWN, (int) > V2DI_FTYPE_V2DI_V2DI_V2DI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v2di_mask, > "__builtin_ia32_vpshrdv_v2di_mask", IX86_BUILTIN_VPSHRDVV2DI_MASK, > UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v2di_maskz, > "__builtin_ia32_vpshrdv_v2di_maskz", IX86_BUILTIN_VPSHRDVV2DI_MASKZ, > UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v4di, "__builtin_ia32_vpshrdv_v4di", > IX86_BUILTIN_VPSHRDVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v4di_mask, "__builtin_ia32_vpshrdv_v4di_mask", > IX86_BUILTIN_VPSHRDVV4DI_MASK, UNKNOWN, (int) > V4DI_FTYPE_V4DI_V4DI_V4DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v4di_maskz, "__builtin_ia32_vpshrdv_v4di_maskz", > IX86_BUILTIN_VPSHRDVV4DI_MASKZ, UNKNOWN, (int) > V4DI_FTYPE_V4DI_V4DI_V4DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v2di, "__builtin_ia32_vpshrdv_v2di", > IX86_BUILTIN_VPSHRDVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v2di_mask, "__builtin_ia32_vpshrdv_v2di_mask", > IX86_BUILTIN_VPSHRDVV2DI_MASK, UNKNOWN, (int) > V2DI_FTYPE_V2DI_V2DI_V2DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshrdv_v2di_maskz, "__builtin_ia32_vpshrdv_v2di_maskz", > IX86_BUILTIN_VPSHRDVV2DI_MASKZ, UNKNOWN, (int) > V2DI_FTYPE_V2DI_V2DI_V2DI_INT) > > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v32hi, > "__builtin_ia32_vpshldv_v32hi", IX86_BUILTIN_VPSHLDVV32HI, UNKNOWN, > (int) V32HI_FTYPE_V32HI_V32HI_V32HI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v32hi_mask, > "__builtin_ia32_vpshldv_v32hi_mask", IX86_BUILTIN_VPSHLDVV32HI_MASK, > UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v32hi_maskz, > "__builtin_ia32_vpshldv_v32hi_maskz", IX86_BUILTIN_VPSHLDVV32HI_MASKZ, > UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v16hi, > "__builtin_ia32_vpshldv_v16hi", IX86_BUILTIN_VPSHLDVV16HI, UNKNOWN, > (int) V16HI_FTYPE_V16HI_V16HI_V16HI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v16hi_mask, > "__builtin_ia32_vpshldv_v16hi_mask", IX86_BUILTIN_VPSHLDVV16HI_MASK, > UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v16hi_maskz, > "__builtin_ia32_vpshldv_v16hi_maskz", IX86_BUILTIN_VPSHLDVV16HI_MASKZ, > UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8hi, > "__builtin_ia32_vpshldv_v8hi", IX86_BUILTIN_VPSHLDVV8HI, UNKNOWN, (int) > V8HI_FTYPE_V8HI_V8HI_V8HI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8hi_mask, > "__builtin_ia32_vpshldv_v8hi_mask", IX86_BUILTIN_VPSHLDVV8HI_MASK, > UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8hi_maskz, > "__builtin_ia32_vpshldv_v8hi_maskz", IX86_BUILTIN_VPSHLDVV8HI_MASKZ, > UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_vpshldv_v32hi_mask, "__builtin_ia32_vpshldv_v32hi_mask", > IX86_BUILTIN_VPSHLDVV32HI_MASK, UNKNOWN, (int) > V32HI_FTYPE_V32HI_V32HI_V32HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_vpshldv_v32hi_maskz, "__builtin_ia32_vpshldv_v32hi_maskz", > IX86_BUILTIN_VPSHLDVV32HI_MASKZ, UNKNOWN, (int) > V32HI_FTYPE_V32HI_V32HI_V32HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v16hi, "__builtin_ia32_vpshldv_v16hi", > IX86_BUILTIN_VPSHLDVV16HI, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_V16HI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v16hi_mask, "__builtin_ia32_vpshldv_v16hi_mask", > IX86_BUILTIN_VPSHLDVV16HI_MASK, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_V16HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v16hi_maskz, "__builtin_ia32_vpshldv_v16hi_maskz", > IX86_BUILTIN_VPSHLDVV16HI_MASKZ, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_V16HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v8hi, "__builtin_ia32_vpshldv_v8hi", > IX86_BUILTIN_VPSHLDVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v8hi_mask, "__builtin_ia32_vpshldv_v8hi_mask", > IX86_BUILTIN_VPSHLDVV8HI_MASK, UNKNOWN, (int) > V8HI_FTYPE_V8HI_V8HI_V8HI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v8hi_maskz, "__builtin_ia32_vpshldv_v8hi_maskz", > IX86_BUILTIN_VPSHLDVV8HI_MASKZ, UNKNOWN, (int) > V8HI_FTYPE_V8HI_V8HI_V8HI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v16si, > "__builtin_ia32_vpshldv_v16si", IX86_BUILTIN_VPSHLDVV16SI, UNKNOWN, (int) > V16SI_FTYPE_V16SI_V16SI_V16SI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v16si_mask, > "__builtin_ia32_vpshldv_v16si_mask", IX86_BUILTIN_VPSHLDVV16SI_MASK, > UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v16si_maskz, > "__builtin_ia32_vpshldv_v16si_maskz", IX86_BUILTIN_VPSHLDVV16SI_MASKZ, > UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8si, > "__builtin_ia32_vpshldv_v8si", IX86_BUILTIN_VPSHLDVV8SI, UNKNOWN, (int) > V8SI_FTYPE_V8SI_V8SI_V8SI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8si_mask, > "__builtin_ia32_vpshldv_v8si_mask", IX86_BUILTIN_VPSHLDVV8SI_MASK, > UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8si_maskz, > "__builtin_ia32_vpshldv_v8si_maskz", IX86_BUILTIN_VPSHLDVV8SI_MASKZ, > UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v4si, > "__builtin_ia32_vpshldv_v4si", IX86_BUILTIN_VPSHLDVV4SI, UNKNOWN, (int) > V4SI_FTYPE_V4SI_V4SI_V4SI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v4si_mask, > "__builtin_ia32_vpshldv_v4si_mask", IX86_BUILTIN_VPSHLDVV4SI_MASK, > UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v4si_maskz, > "__builtin_ia32_vpshldv_v4si_maskz", IX86_BUILTIN_VPSHLDVV4SI_MASKZ, > UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v8si, "__builtin_ia32_vpshldv_v8si", > IX86_BUILTIN_VPSHLDVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v8si_mask, "__builtin_ia32_vpshldv_v8si_mask", > IX86_BUILTIN_VPSHLDVV8SI_MASK, UNKNOWN, (int) > V8SI_FTYPE_V8SI_V8SI_V8SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v8si_maskz, "__builtin_ia32_vpshldv_v8si_maskz", > IX86_BUILTIN_VPSHLDVV8SI_MASKZ, UNKNOWN, (int) > V8SI_FTYPE_V8SI_V8SI_V8SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v4si, "__builtin_ia32_vpshldv_v4si", > IX86_BUILTIN_VPSHLDVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v4si_mask, "__builtin_ia32_vpshldv_v4si_mask", > IX86_BUILTIN_VPSHLDVV4SI_MASK, UNKNOWN, (int) > V4SI_FTYPE_V4SI_V4SI_V4SI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v4si_maskz, "__builtin_ia32_vpshldv_v4si_maskz", > IX86_BUILTIN_VPSHLDVV4SI_MASKZ, UNKNOWN, (int) > V4SI_FTYPE_V4SI_V4SI_V4SI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8di, > "__builtin_ia32_vpshldv_v8di", IX86_BUILTIN_VPSHLDVV8DI, UNKNOWN, (int) > V8DI_FTYPE_V8DI_V8DI_V8DI) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8di_mask, > "__builtin_ia32_vpshldv_v8di_mask", IX86_BUILTIN_VPSHLDVV8DI_MASK, > UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT) > BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v8di_maskz, > "__builtin_ia32_vpshldv_v8di_maskz", IX86_BUILTIN_VPSHLDVV8DI_MASKZ, > UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v4di, > "__builtin_ia32_vpshldv_v4di", IX86_BUILTIN_VPSHLDVV4DI, UNKNOWN, (int) > V4DI_FTYPE_V4DI_V4DI_V4DI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v4di_mask, > "__builtin_ia32_vpshldv_v4di_mask", IX86_BUILTIN_VPSHLDVV4DI_MASK, > UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v4di_maskz, > "__builtin_ia32_vpshldv_v4di_maskz", IX86_BUILTIN_VPSHLDVV4DI_MASKZ, > UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v2di, > "__builtin_ia32_vpshldv_v2di", IX86_BUILTIN_VPSHLDVV2DI, UNKNOWN, (int) > V2DI_FTYPE_V2DI_V2DI_V2DI) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v2di_mask, > "__builtin_ia32_vpshldv_v2di_mask", IX86_BUILTIN_VPSHLDVV2DI_MASK, > UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT) > -BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v2di_maskz, > "__builtin_ia32_vpshldv_v2di_maskz", IX86_BUILTIN_VPSHLDVV2DI_MASKZ, > UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v4di, "__builtin_ia32_vpshldv_v4di", > IX86_BUILTIN_VPSHLDVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v4di_mask, "__builtin_ia32_vpshldv_v4di_mask", > IX86_BUILTIN_VPSHLDVV4DI_MASK, UNKNOWN, (int) > V4DI_FTYPE_V4DI_V4DI_V4DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v4di_maskz, "__builtin_ia32_vpshldv_v4di_maskz", > IX86_BUILTIN_VPSHLDVV4DI_MASKZ, UNKNOWN, (int) > V4DI_FTYPE_V4DI_V4DI_V4DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v2di, "__builtin_ia32_vpshldv_v2di", > IX86_BUILTIN_VPSHLDVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v2di_mask, "__builtin_ia32_vpshldv_v2di_mask", > IX86_BUILTIN_VPSHLDVV2DI_MASK, UNKNOWN, (int) > V2DI_FTYPE_V2DI_V2DI_V2DI_INT) > +BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpshldv_v2di_maskz, "__builtin_ia32_vpshldv_v2di_maskz", > IX86_BUILTIN_VPSHLDVV2DI_MASKZ, UNKNOWN, (int) > V2DI_FTYPE_V2DI_V2DI_V2DI_INT) > > /* GFNI */ > BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v64qi, > "__builtin_ia32_vgf2p8affineinvqb_v64qi", > IX86_BUILTIN_VGF2P8AFFINEINVQB512, UNKNOWN, (int) > V64QI_FTYPE_V64QI_V64QI_INT) > @@ -2596,6 +2596,40 @@ BDESC (OPTION_MASK_ISA_VPCLMULQDQ | OPTI > BDESC (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_AVX, > CODE_FOR_vpclmulqdq_v4di, "__builtin_ia32_vpclmulqdq_v4di", > IX86_BUILTIN_VPCLMULQDQ4, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT) > BDESC (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_AVX512F, > CODE_FOR_vpclmulqdq_v8di, "__builtin_ia32_vpclmulqdq_v8di", > IX86_BUILTIN_VPCLMULQDQ8, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT) > > +/* VPOPCNTDQ */ > +BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ, CODE_FOR_vpopcountv16si, > "__builtin_ia32_vpopcountd_v16si", IX86_BUILTIN_VPOPCOUNTDV16SI, > UNKNOWN, (int) V16SI_FTYPE_V16SI) > +BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ, > CODE_FOR_vpopcountv16si_mask, "__builtin_ia32_vpopcountd_v16si_mask", > IX86_BUILTIN_VPOPCOUNTDV16SI_MASK, UNKNOWN, (int) > V16SI_FTYPE_V16SI_V16SI_UHI) > +BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ, CODE_FOR_vpopcountv8di, > "__builtin_ia32_vpopcountq_v8di", IX86_BUILTIN_VPOPCOUNTQV8DI, > UNKNOWN, (int) V8DI_FTYPE_V8DI) > +BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ, > CODE_FOR_vpopcountv8di_mask, "__builtin_ia32_vpopcountq_v8di_mask", > IX86_BUILTIN_VPOPCOUNTQV8DI_MASK, UNKNOWN, (int) > V8DI_FTYPE_V8DI_V8DI_UQI) > + > +BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv4di, > "__builtin_ia32_vpopcountq_v4di", IX86_BUILTIN_VPOPCOUNTQV4DI, > UNKNOWN, (int) V4DI_FTYPE_V4DI) > +BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv4di_mask, > "__builtin_ia32_vpopcountq_v4di_mask", > IX86_BUILTIN_VPOPCOUNTQV4DI_MASK, UNKNOWN, (int) > V4DI_FTYPE_V4DI_V4DI_UQI) > +BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv2di, > "__builtin_ia32_vpopcountq_v2di", IX86_BUILTIN_VPOPCOUNTQV2DI, > UNKNOWN, (int) V2DI_FTYPE_V2DI) > +BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv2di_mask, > "__builtin_ia32_vpopcountq_v2di_mask", > IX86_BUILTIN_VPOPCOUNTQV2DI_MASK, UNKNOWN, (int) > V2DI_FTYPE_V2DI_V2DI_UQI) > +BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv4si, > "__builtin_ia32_vpopcountd_v4si", IX86_BUILTIN_VPOPCOUNTDV4SI, > UNKNOWN, (int) V4SI_FTYPE_V4SI) > +BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv4si_mask, > "__builtin_ia32_vpopcountd_v4si_mask", > IX86_BUILTIN_VPOPCOUNTDV4SI_MASK, UNKNOWN, (int) > V4SI_FTYPE_V4SI_V4SI_UHI) > +BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv8si, > "__builtin_ia32_vpopcountd_v8si", IX86_BUILTIN_VPOPCOUNTDV8SI, > UNKNOWN, (int) V8SI_FTYPE_V8SI) > +BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv8si_mask, > "__builtin_ia32_vpopcountd_v8si_mask", > IX86_BUILTIN_VPOPCOUNTDV8SI_MASK, UNKNOWN, (int) > V8SI_FTYPE_V8SI_V8SI_UHI) > + > +/* BITALG */ > +BDESC (OPTION_MASK_ISA_AVX512BITALG, CODE_FOR_vpopcountv64qi, > "__builtin_ia32_vpopcountb_v64qi", IX86_BUILTIN_VPOPCOUNTBV64QI, > UNKNOWN, (int) V64QI_FTYPE_V64QI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_vpopcountv64qi_mask, "__builtin_ia32_vpopcountb_v64qi_mask", > IX86_BUILTIN_VPOPCOUNTBV64QI_MASK, UNKNOWN, (int) > V64QI_FTYPE_V64QI_V64QI_UDI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpopcountv32qi, "__builtin_ia32_vpopcountb_v32qi", > IX86_BUILTIN_VPOPCOUNTBV32QI, UNKNOWN, (int) V32QI_FTYPE_V32QI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL | > OPTION_MASK_ISA_AVX512BW, CODE_FOR_vpopcountv32qi_mask, > "__builtin_ia32_vpopcountb_v32qi_mask", > IX86_BUILTIN_VPOPCOUNTBV32QI_MASK, UNKNOWN, (int) > V32QI_FTYPE_V32QI_V32QI_USI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpopcountv16qi, "__builtin_ia32_vpopcountb_v16qi", > IX86_BUILTIN_VPOPCOUNTBV16QI, UNKNOWN, (int) V16QI_FTYPE_V16QI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpopcountv16qi_mask, "__builtin_ia32_vpopcountb_v16qi_mask", > IX86_BUILTIN_VPOPCOUNTBV16QI_MASK, UNKNOWN, (int) > V16QI_FTYPE_V16QI_V16QI_UHI) > + > +BDESC (OPTION_MASK_ISA_AVX512BITALG, CODE_FOR_vpopcountv32hi, > "__builtin_ia32_vpopcountw_v32hi", IX86_BUILTIN_VPOPCOUNTWV32HI, > UNKNOWN, (int) V32HI_FTYPE_V32HI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_vpopcountv32hi_mask, "__builtin_ia32_vpopcountw_v32hi_mask", > IX86_BUILTIN_VPOPCOUNTQV32HI_MASK, UNKNOWN, (int) > V32HI_FTYPE_V32HI_V32HI_USI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpopcountv16hi, "__builtin_ia32_vpopcountw_v16hi", > IX86_BUILTIN_VPOPCOUNTWV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpopcountv16hi_mask, "__builtin_ia32_vpopcountw_v16hi_mask", > IX86_BUILTIN_VPOPCOUNTQV16HI_MASK, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_UHI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpopcountv8hi, "__builtin_ia32_vpopcountw_v8hi", > IX86_BUILTIN_VPOPCOUNTWV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_vpopcountv8hi_mask, "__builtin_ia32_vpopcountw_v8hi_mask", > IX86_BUILTIN_VPOPCOUNTQV8HI_MASK, UNKNOWN, (int) > V8HI_FTYPE_V8HI_V8HI_UQI) > + > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW, > CODE_FOR_avx512vl_vpshufbitqmbv8di_mask, > "__builtin_ia32_vpshufbitqmb512_mask", > IX86_BUILTIN_VPSHUFBITQMB512_MASK, UNKNOWN, (int) > UQI_FTYPE_V8DI_V8DI_UQI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL | > OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512vl_vpshufbitqmbv4di_mask, > "__builtin_ia32_vpshufbitqmb256_mask", > IX86_BUILTIN_VPSHUFBITQMB256_MASK, UNKNOWN, (int) > USI_FTYPE_V4DI_V4DI_USI) > +BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_avx512vl_vpshufbitqmbv2di_mask, > "__builtin_ia32_vpshufbitqmb128_mask", > IX86_BUILTIN_VPSHUFBITQMB128_MASK, UNKNOWN, (int) > UHI_FTYPE_V2DI_V2DI_UHI) > + > /* Builtins with rounding support. */ > BDESC_END (ARGS, ROUND_ARGS) > > @@ -2783,20 +2817,6 @@ BDESC (OPTION_MASK_ISA_AVX5124VNNIW, COD > BDESC (OPTION_MASK_ISA_AVX5124VNNIW, > CODE_FOR_avx5124vnniw_vp4dpwssd_mask, > "__builtin_ia32_vp4dpwssd_mask", IX86_BUILTIN_4DPWSSD_MASK, > UNKNOWN, (int) > V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI_V16SI_UHI) > BDESC (OPTION_MASK_ISA_AVX5124VNNIW, > CODE_FOR_avx5124vnniw_vp4dpwssds, "__builtin_ia32_vp4dpwssds", > IX86_BUILTIN_4DPWSSDS, UNKNOWN, (int) > V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI) > BDESC (OPTION_MASK_ISA_AVX5124VNNIW, > CODE_FOR_avx5124vnniw_vp4dpwssds_mask, > "__builtin_ia32_vp4dpwssds_mask", IX86_BUILTIN_4DPWSSDS_MASK, > UNKNOWN, (int) > V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI_V16SI_UHI) > -BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ, CODE_FOR_vpopcountv16si, > "__builtin_ia32_vpopcountd_v16si", IX86_BUILTIN_VPOPCOUNTDV16SI, > UNKNOWN, (int) V16SI_FTYPE_V16SI) > -BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ, > CODE_FOR_vpopcountv16si_mask, "__builtin_ia32_vpopcountd_v16si_mask", > IX86_BUILTIN_VPOPCOUNTDV16SI_MASK, UNKNOWN, (int) > V16SI_FTYPE_V16SI_V16SI_UHI) > -BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ, CODE_FOR_vpopcountv8di, > "__builtin_ia32_vpopcountq_v8di", IX86_BUILTIN_VPOPCOUNTQV8DI, > UNKNOWN, (int) V8DI_FTYPE_V8DI) > -BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ, > CODE_FOR_vpopcountv8di_mask, "__builtin_ia32_vpopcountq_v8di_mask", > IX86_BUILTIN_VPOPCOUNTQV8DI_MASK, UNKNOWN, (int) > V8DI_FTYPE_V8DI_V8DI_UQI) > - > -BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv4di, > "__builtin_ia32_vpopcountq_v4di", IX86_BUILTIN_VPOPCOUNTQV4DI, > UNKNOWN, (int) V4DI_FTYPE_V4DI) > -BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv4di_mask, > "__builtin_ia32_vpopcountq_v4di_mask", > IX86_BUILTIN_VPOPCOUNTQV4DI_MASK, UNKNOWN, (int) > V4DI_FTYPE_V4DI_V4DI_UQI) > -BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv2di, > "__builtin_ia32_vpopcountq_v2di", IX86_BUILTIN_VPOPCOUNTQV2DI, > UNKNOWN, (int) V2DI_FTYPE_V2DI) > -BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv2di_mask, > "__builtin_ia32_vpopcountq_v2di_mask", > IX86_BUILTIN_VPOPCOUNTQV2DI_MASK, UNKNOWN, (int) > V2DI_FTYPE_V2DI_V2DI_UQI) > -BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv4si, > "__builtin_ia32_vpopcountd_v4si", IX86_BUILTIN_VPOPCOUNTDV4SI, > UNKNOWN, (int) V4SI_FTYPE_V4SI) > -BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv4si_mask, > "__builtin_ia32_vpopcountd_v4si_mask", > IX86_BUILTIN_VPOPCOUNTDV4SI_MASK, UNKNOWN, (int) > V4SI_FTYPE_V4SI_V4SI_UHI) > -BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv8si, > "__builtin_ia32_vpopcountd_v8si", IX86_BUILTIN_VPOPCOUNTDV8SI, > UNKNOWN, (int) V8SI_FTYPE_V8SI) > -BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv8si_mask, > "__builtin_ia32_vpopcountd_v8si_mask", > IX86_BUILTIN_VPOPCOUNTDV8SI_MASK, UNKNOWN, (int) > V8SI_FTYPE_V8SI_V8SI_UHI) > - > > /* RDPID */ > BDESC (OPTION_MASK_ISA_RDPID, CODE_FOR_rdpid, "__builtin_ia32_rdpid", > IX86_BUILTIN_RDPID, UNKNOWN, (int) UNSIGNED_FTYPE_VOID) > @@ -2815,24 +2835,6 @@ BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_va > BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenclast_v32qi, > "__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32, > UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) > BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenclast_v64qi, > "__builtin_ia32_vaesenclast_v64qi", IX86_BUILTIN_VAESENCLAST64, > UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) > > -/* BITALG */ > -BDESC (OPTION_MASK_ISA_AVX512BITALG, CODE_FOR_vpopcountv64qi, > "__builtin_ia32_vpopcountb_v64qi", IX86_BUILTIN_VPOPCOUNTBV64QI, > UNKNOWN, (int) V64QI_FTYPE_V64QI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG, > CODE_FOR_vpopcountv64qi_mask, "__builtin_ia32_vpopcountb_v64qi_mask", > IX86_BUILTIN_VPOPCOUNTBV64QI_MASK, UNKNOWN, (int) > V64QI_FTYPE_V64QI_V64QI_UDI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG, CODE_FOR_vpopcountv32qi, > "__builtin_ia32_vpopcountb_v32qi", IX86_BUILTIN_VPOPCOUNTBV32QI, > UNKNOWN, (int) V32QI_FTYPE_V32QI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG, > CODE_FOR_vpopcountv32qi_mask, "__builtin_ia32_vpopcountb_v32qi_mask", > IX86_BUILTIN_VPOPCOUNTBV32QI_MASK, UNKNOWN, (int) > V32QI_FTYPE_V32QI_V32QI_USI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG, CODE_FOR_vpopcountv16qi, > "__builtin_ia32_vpopcountb_v16qi", IX86_BUILTIN_VPOPCOUNTBV16QI, > UNKNOWN, (int) V16QI_FTYPE_V16QI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG, > CODE_FOR_vpopcountv16qi_mask, "__builtin_ia32_vpopcountb_v16qi_mask", > IX86_BUILTIN_VPOPCOUNTBV16QI_MASK, UNKNOWN, (int) > V16QI_FTYPE_V16QI_V16QI_UHI) > - > -BDESC (OPTION_MASK_ISA_AVX512BITALG, CODE_FOR_vpopcountv32hi, > "__builtin_ia32_vpopcountw_v32hi", IX86_BUILTIN_VPOPCOUNTWV32HI, > UNKNOWN, (int) V32HI_FTYPE_V32HI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG, > CODE_FOR_vpopcountv32hi_mask, "__builtin_ia32_vpopcountw_v32hi_mask", > IX86_BUILTIN_VPOPCOUNTQV32HI_MASK, UNKNOWN, (int) > V32HI_FTYPE_V32HI_V32HI_USI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG, CODE_FOR_vpopcountv16hi, > "__builtin_ia32_vpopcountw_v16hi", IX86_BUILTIN_VPOPCOUNTWV16HI, > UNKNOWN, (int) V16HI_FTYPE_V16HI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG, > CODE_FOR_vpopcountv16hi_mask, "__builtin_ia32_vpopcountw_v16hi_mask", > IX86_BUILTIN_VPOPCOUNTQV16HI_MASK, UNKNOWN, (int) > V16HI_FTYPE_V16HI_V16HI_UHI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG, CODE_FOR_vpopcountv8hi, > "__builtin_ia32_vpopcountw_v8hi", IX86_BUILTIN_VPOPCOUNTWV8HI, > UNKNOWN, (int) V8HI_FTYPE_V8HI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG, CODE_FOR_vpopcountv8hi_mask, > "__builtin_ia32_vpopcountw_v8hi_mask", > IX86_BUILTIN_VPOPCOUNTQV8HI_MASK, UNKNOWN, (int) > V8HI_FTYPE_V8HI_V8HI_UQI) > - > -BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_avx512vl_vpshufbitqmbv2di_mask, > "__builtin_ia32_vpshufbitqmb128_mask", > IX86_BUILTIN_VPSHUFBITQMB128_MASK, UNKNOWN, (int) > UHI_FTYPE_V2DI_V2DI_UHI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, > CODE_FOR_avx512vl_vpshufbitqmbv4di_mask, > "__builtin_ia32_vpshufbitqmb256_mask", > IX86_BUILTIN_VPSHUFBITQMB256_MASK, UNKNOWN, (int) > USI_FTYPE_V4DI_V4DI_USI) > -BDESC (OPTION_MASK_ISA_AVX512BITALG, > CODE_FOR_avx512vl_vpshufbitqmbv8di_mask, > "__builtin_ia32_vpshufbitqmb512_mask", > IX86_BUILTIN_VPSHUFBITQMB512_MASK, UNKNOWN, (int) > UQI_FTYPE_V8DI_V8DI_UQI) > BDESC_END (ARGS2, MPX) > > /* Builtins for MPX. */ > --- gcc/config/i386/avx512vbmi2intrin.h.jj 2017-11-30 > 09:42:46.000000000 +0100 > +++ gcc/config/i386/avx512vbmi2intrin.h 2017-12-22 > 17:37:50.395929142 +0100 > @@ -28,127 +28,11 @@ > #ifndef __AVX512VBMI2INTRIN_H_INCLUDED > #define __AVX512VBMI2INTRIN_H_INCLUDED > > -#if !defined(__AVX512VBMI2__) || !defined(__AVX512BW__) > +#if !defined(__AVX512VBMI2__) > #pragma GCC push_options > -#pragma GCC target("avx512vbmi2,avx512bw") > -#define __DISABLE_AVX512VBMI2BW__ > -#endif /* __AVX512VBMI2BW__ */ > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_mask_compress_epi8 (__m512i __A, __mmask64 __B, __m512i __C) > -{ > - return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi)__C, > - (__v64qi)__A, > (__mmask64)__B); > -} > - > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_maskz_compress_epi8 (__mmask64 __A, __m512i __B) > -{ > - return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi)__B, > - (__v64qi)_mm512_setzero_si512 (), (__mmask64)__A); > -} > - > - > -extern __inline void > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_mask_compressstoreu_epi8 (void * __A, __mmask64 __B, __m512i > __C) > -{ > - __builtin_ia32_compressstoreuqi512_mask ((__v64qi *) __A, (__v64qi) __C, > - (__mmask64) __B); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_mask_compress_epi16 (__m512i __A, __mmask32 __B, __m512i __C) > -{ > - return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi)__C, > - (__v32hi)__A, > (__mmask32)__B); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_maskz_compress_epi16 (__mmask32 __A, __m512i __B) > -{ > - return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi)__B, > - (__v32hi)_mm512_setzero_si512 (), (__mmask32)__A); > -} > - > -extern __inline void > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_mask_compressstoreu_epi16 (void * __A, __mmask32 __B, __m512i > __C) > -{ > - __builtin_ia32_compressstoreuhi512_mask ((__v32hi *) __A, (__v32hi) __C, > - (__mmask32) __B); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_mask_expand_epi8 (__m512i __A, __mmask64 __B, __m512i __C) > -{ > - return (__m512i) __builtin_ia32_expandqi512_mask ((__v64qi) __C, > - (__v64qi) __A, > - (__mmask64) __B); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_maskz_expand_epi8 (__mmask64 __A, __m512i __B) > -{ > - return (__m512i) __builtin_ia32_expandqi512_maskz ((__v64qi) __B, > - (__v64qi) _mm512_setzero_si512 (), (__mmask64) __A); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_mask_expandloadu_epi8 (__m512i __A, __mmask64 __B, const void > * __C) > -{ > - return (__m512i) __builtin_ia32_expandloadqi512_mask ((const __v64qi *) > __C, > - (__v64qi) __A, (__mmask64) __B); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_maskz_expandloadu_epi8 (__mmask64 __A, const void * __B) > -{ > - return (__m512i) __builtin_ia32_expandloadqi512_maskz ((const __v64qi *) > __B, > - (__v64qi) _mm512_setzero_si512 (), (__mmask64) __A); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_mask_expand_epi16 (__m512i __A, __mmask32 __B, __m512i __C) > -{ > - return (__m512i) __builtin_ia32_expandhi512_mask ((__v32hi) __C, > - (__v32hi) __A, > - (__mmask32) __B); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_maskz_expand_epi16 (__mmask32 __A, __m512i __B) > -{ > - return (__m512i) __builtin_ia32_expandhi512_maskz ((__v32hi) __B, > - (__v32hi) _mm512_setzero_si512 (), (__mmask32) __A); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_mask_expandloadu_epi16 (__m512i __A, __mmask32 __B, const void > * __C) > -{ > - return (__m512i) __builtin_ia32_expandloadhi512_mask ((const __v32hi *) > __C, > - (__v32hi) __A, (__mmask32) __B); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_maskz_expandloadu_epi16 (__mmask32 __A, const void * __B) > -{ > - return (__m512i) __builtin_ia32_expandloadhi512_maskz ((const __v32hi *) > __B, > - (__v32hi) _mm512_setzero_si512 (), (__mmask32) __A); > -} > +#pragma GCC target("avx512vbmi2") > +#define __DISABLE_AVX512VBMI2__ > +#endif /* __AVX512VBMI2__ */ > > #ifdef __OPTIMIZE__ > extern __inline __m512i > @@ -161,23 +45,6 @@ _mm512_shrdi_epi16 (__m512i __A, __m512i > > extern __inline __m512i > __attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_mask_shrdi_epi16 (__m512i __A, __mmask32 __B, __m512i __C, > __m512i __D, > - int __E) > -{ > - return (__m512i)__builtin_ia32_vpshrd_v32hi_mask ((__v32hi)__C, > - (__v32hi) __D, __E, (__v32hi) __A, (__mmask32)__B); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_maskz_shrdi_epi16 (__mmask32 __A, __m512i __B, __m512i __C, int > __D) > -{ > - return (__m512i)__builtin_ia32_vpshrd_v32hi_mask ((__v32hi)__B, > - (__v32hi) __C, __D, (__v32hi) _mm512_setzero_si512 (), > (__mmask32)__A); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > _mm512_shrdi_epi32 (__m512i __A, __m512i __B, int __C) > { > return (__m512i) __builtin_ia32_vpshrd_v16si ((__v16si)__A, (__v16si) __B, > @@ -235,23 +102,6 @@ _mm512_shldi_epi16 (__m512i __A, __m512i > > extern __inline __m512i > __attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_mask_shldi_epi16 (__m512i __A, __mmask32 __B, __m512i __C, > __m512i __D, > - int __E) > -{ > - return (__m512i)__builtin_ia32_vpshld_v32hi_mask ((__v32hi)__C, > - (__v32hi) __D, __E, (__v32hi) __A, (__mmask32)__B); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_maskz_shldi_epi16 (__mmask32 __A, __m512i __B, __m512i __C, int > __D) > -{ > - return (__m512i)__builtin_ia32_vpshld_v32hi_mask ((__v32hi)__B, > - (__v32hi) __C, __D, (__v32hi) _mm512_setzero_si512 (), > (__mmask32)__A); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > _mm512_shldi_epi32 (__m512i __A, __m512i __B, int __C) > { > return (__m512i) __builtin_ia32_vpshld_v16si ((__v16si)__A, (__v16si) __B, > @@ -302,13 +152,6 @@ _mm512_maskz_shldi_epi64 (__mmask8 __A, > #define _mm512_shrdi_epi16(A, B, C) \ > ((__m512i) __builtin_ia32_vpshrd_v32hi ((__v32hi)(__m512i)(A), \ > (__v32hi)(__m512i)(B),(int)(C)) > -#define _mm512_mask_shrdi_epi16(A, B, C, D, E) \ > - ((__m512i) __builtin_ia32_vpshrd_v32hi_mask ((__v32hi)(__m512i)(C), \ > - (__v32hi)(__m512i)(D), (int)(E), (__v32hi)(__m512i)(A),(__mmask32)(B)) > -#define _mm512_maskz_shrdi_epi16(A, B, C, D) \ > - ((__m512i) __builtin_ia32_vpshrd_v32hi_mask ((__v32hi)(__m512i)(B), \ > - (__v32hi)(__m512i)(C),(int)(D), \ > - (__v32hi)(__m512i)_mm512_setzero_si512 (), (__mmask32)(A)) > #define _mm512_shrdi_epi32(A, B, C) \ > ((__m512i) __builtin_ia32_vpshrd_v16si ((__v16si)(__m512i)(A), \ > (__v16si)(__m512i)(B),(int)(C)) > @@ -332,13 +175,6 @@ _mm512_maskz_shldi_epi64 (__mmask8 __A, > #define _mm512_shldi_epi16(A, B, C) \ > ((__m512i) __builtin_ia32_vpshld_v32hi ((__v32hi)(__m512i)(A), \ > (__v32hi)(__m512i)(B),(int)(C)) > -#define _mm512_mask_shldi_epi16(A, B, C, D, E) \ > - ((__m512i) __builtin_ia32_vpshld_v32hi_mask ((__v32hi)(__m512i)(C), \ > - (__v32hi)(__m512i)(D), (int)(E), (__v32hi)(__m512i)(A),(__mmask32)(B)) > -#define _mm512_maskz_shldi_epi16(A, B, C, D) \ > - ((__m512i) __builtin_ia32_vpshld_v32hi_mask ((__v32hi)(__m512i)(B), \ > - (__v32hi)(__m512i)(C),(int)(D), \ > - (__v32hi)(__m512i)_mm512_setzero_si512 (), (__mmask32)(A)) > #define _mm512_shldi_epi32(A, B, C) \ > ((__m512i) __builtin_ia32_vpshld_v16si ((__v16si)(__m512i)(A), \ > (__v16si)(__m512i)(B),(int)(C)) > @@ -371,22 +207,6 @@ _mm512_shrdv_epi16 (__m512i __A, __m512i > > extern __inline __m512i > __attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_mask_shrdv_epi16 (__m512i __A, __mmask32 __B, __m512i __C, > __m512i __D) > -{ > - return (__m512i)__builtin_ia32_vpshrdv_v32hi_mask ((__v32hi)__A, > - (__v32hi) __C, (__v32hi) __D, > (__mmask32)__B); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_maskz_shrdv_epi16 (__mmask32 __A, __m512i __B, __m512i __C, > __m512i __D) > -{ > - return (__m512i)__builtin_ia32_vpshrdv_v32hi_maskz ((__v32hi)__B, > - (__v32hi) __C, (__v32hi) __D, > (__mmask32)__A); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > _mm512_shrdv_epi32 (__m512i __A, __m512i __B, __m512i __C) > { > return (__m512i) __builtin_ia32_vpshrdv_v16si ((__v16si)__A, (__v16si) __B, > @@ -442,22 +262,6 @@ _mm512_shldv_epi16 (__m512i __A, __m512i > > extern __inline __m512i > __attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_mask_shldv_epi16 (__m512i __A, __mmask32 __B, __m512i __C, > __m512i __D) > -{ > - return (__m512i)__builtin_ia32_vpshldv_v32hi_mask ((__v32hi)__A, > - (__v32hi) __C, (__v32hi) __D, > (__mmask32)__B); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm512_maskz_shldv_epi16 (__mmask32 __A, __m512i __B, __m512i __C, > __m512i __D) > -{ > - return (__m512i)__builtin_ia32_vpshldv_v32hi_maskz ((__v32hi)__B, > - (__v32hi) __C, (__v32hi) __D, > (__mmask32)__A); > -} > - > -extern __inline __m512i > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > _mm512_shldv_epi32 (__m512i __A, __m512i __B, __m512i __C) > { > return (__m512i) __builtin_ia32_vpshldv_v16si ((__v16si)__A, (__v16si) __B, > @@ -504,6 +308,218 @@ _mm512_maskz_shldv_epi64 (__mmask8 __A, > (__v8di) __D, (__mmask8)__A); > } > > +#ifdef __DISABLE_AVX512VBMI2__ > +#undef __DISABLE_AVX512VBMI2__ > + > +#pragma GCC pop_options > +#endif /* __DISABLE_AVX512VBMI2__ */ > + > +#if !defined(__AVX512VBMI2__) || !defined(__AVX512BW__) > +#pragma GCC push_options > +#pragma GCC target("avx512vbmi2,avx512bw") > +#define __DISABLE_AVX512VBMI2BW__ > +#endif /* __AVX512VBMI2BW__ */ > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_mask_compress_epi8 (__m512i __A, __mmask64 __B, __m512i __C) > +{ > + return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi)__C, > + (__v64qi)__A, > (__mmask64)__B); > +} > + > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_maskz_compress_epi8 (__mmask64 __A, __m512i __B) > +{ > + return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi)__B, > + (__v64qi)_mm512_setzero_si512 (), (__mmask64)__A); > +} > + > + > +extern __inline void > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_mask_compressstoreu_epi8 (void * __A, __mmask64 __B, __m512i > __C) > +{ > + __builtin_ia32_compressstoreuqi512_mask ((__v64qi *) __A, (__v64qi) __C, > + (__mmask64) __B); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_mask_compress_epi16 (__m512i __A, __mmask32 __B, __m512i > __C) > +{ > + return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi)__C, > + (__v32hi)__A, > (__mmask32)__B); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_maskz_compress_epi16 (__mmask32 __A, __m512i __B) > +{ > + return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi)__B, > + (__v32hi)_mm512_setzero_si512 (), (__mmask32)__A); > +} > + > +extern __inline void > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_mask_compressstoreu_epi16 (void * __A, __mmask32 __B, __m512i > __C) > +{ > + __builtin_ia32_compressstoreuhi512_mask ((__v32hi *) __A, (__v32hi) __C, > + (__mmask32) __B); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_mask_expand_epi8 (__m512i __A, __mmask64 __B, __m512i __C) > +{ > + return (__m512i) __builtin_ia32_expandqi512_mask ((__v64qi) __C, > + (__v64qi) __A, > + (__mmask64) __B); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_maskz_expand_epi8 (__mmask64 __A, __m512i __B) > +{ > + return (__m512i) __builtin_ia32_expandqi512_maskz ((__v64qi) __B, > + (__v64qi) _mm512_setzero_si512 (), (__mmask64) __A); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_mask_expandloadu_epi8 (__m512i __A, __mmask64 __B, const void > * __C) > +{ > + return (__m512i) __builtin_ia32_expandloadqi512_mask ((const __v64qi *) > __C, > + (__v64qi) __A, (__mmask64) __B); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_maskz_expandloadu_epi8 (__mmask64 __A, const void * __B) > +{ > + return (__m512i) __builtin_ia32_expandloadqi512_maskz ((const __v64qi *) > __B, > + (__v64qi) _mm512_setzero_si512 (), (__mmask64) __A); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_mask_expand_epi16 (__m512i __A, __mmask32 __B, __m512i __C) > +{ > + return (__m512i) __builtin_ia32_expandhi512_mask ((__v32hi) __C, > + (__v32hi) __A, > + (__mmask32) __B); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_maskz_expand_epi16 (__mmask32 __A, __m512i __B) > +{ > + return (__m512i) __builtin_ia32_expandhi512_maskz ((__v32hi) __B, > + (__v32hi) _mm512_setzero_si512 (), (__mmask32) __A); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_mask_expandloadu_epi16 (__m512i __A, __mmask32 __B, const > void * __C) > +{ > + return (__m512i) __builtin_ia32_expandloadhi512_mask ((const __v32hi *) > __C, > + (__v32hi) __A, (__mmask32) __B); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_maskz_expandloadu_epi16 (__mmask32 __A, const void * __B) > +{ > + return (__m512i) __builtin_ia32_expandloadhi512_maskz ((const __v32hi *) > __B, > + (__v32hi) _mm512_setzero_si512 (), (__mmask32) __A); > +} > + > +#ifdef __OPTIMIZE__ > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_mask_shrdi_epi16 (__m512i __A, __mmask32 __B, __m512i __C, > __m512i __D, > + int __E) > +{ > + return (__m512i)__builtin_ia32_vpshrd_v32hi_mask ((__v32hi)__C, > + (__v32hi) __D, __E, (__v32hi) __A, (__mmask32)__B); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_maskz_shrdi_epi16 (__mmask32 __A, __m512i __B, __m512i __C, int > __D) > +{ > + return (__m512i)__builtin_ia32_vpshrd_v32hi_mask ((__v32hi)__B, > + (__v32hi) __C, __D, (__v32hi) _mm512_setzero_si512 (), > (__mmask32)__A); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_mask_shldi_epi16 (__m512i __A, __mmask32 __B, __m512i __C, > __m512i __D, > + int __E) > +{ > + return (__m512i)__builtin_ia32_vpshld_v32hi_mask ((__v32hi)__C, > + (__v32hi) __D, __E, (__v32hi) __A, (__mmask32)__B); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_maskz_shldi_epi16 (__mmask32 __A, __m512i __B, __m512i __C, int > __D) > +{ > + return (__m512i)__builtin_ia32_vpshld_v32hi_mask ((__v32hi)__B, > + (__v32hi) __C, __D, (__v32hi) _mm512_setzero_si512 (), > (__mmask32)__A); > +} > + > +#else > +#define _mm512_mask_shrdi_epi16(A, B, C, D, E) \ > + ((__m512i) __builtin_ia32_vpshrd_v32hi_mask ((__v32hi)(__m512i)(C), \ > + (__v32hi)(__m512i)(D), (int)(E), (__v32hi)(__m512i)(A),(__mmask32)(B)) > +#define _mm512_maskz_shrdi_epi16(A, B, C, D) \ > + ((__m512i) __builtin_ia32_vpshrd_v32hi_mask ((__v32hi)(__m512i)(B), \ > + (__v32hi)(__m512i)(C),(int)(D), \ > + (__v32hi)(__m512i)_mm512_setzero_si512 (), (__mmask32)(A)) > +#define _mm512_mask_shldi_epi16(A, B, C, D, E) \ > + ((__m512i) __builtin_ia32_vpshld_v32hi_mask ((__v32hi)(__m512i)(C), \ > + (__v32hi)(__m512i)(D), (int)(E), (__v32hi)(__m512i)(A),(__mmask32)(B)) > +#define _mm512_maskz_shldi_epi16(A, B, C, D) \ > + ((__m512i) __builtin_ia32_vpshld_v32hi_mask ((__v32hi)(__m512i)(B), \ > + (__v32hi)(__m512i)(C),(int)(D), \ > + (__v32hi)(__m512i)_mm512_setzero_si512 (), (__mmask32)(A)) > +#endif > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_mask_shrdv_epi16 (__m512i __A, __mmask32 __B, __m512i __C, > __m512i __D) > +{ > + return (__m512i)__builtin_ia32_vpshrdv_v32hi_mask ((__v32hi)__A, > + (__v32hi) __C, (__v32hi) __D, > (__mmask32)__B); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_maskz_shrdv_epi16 (__mmask32 __A, __m512i __B, __m512i __C, > __m512i __D) > +{ > + return (__m512i)__builtin_ia32_vpshrdv_v32hi_maskz ((__v32hi)__B, > + (__v32hi) __C, (__v32hi) __D, > (__mmask32)__A); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_mask_shldv_epi16 (__m512i __A, __mmask32 __B, __m512i __C, > __m512i __D) > +{ > + return (__m512i)__builtin_ia32_vpshldv_v32hi_mask ((__v32hi)__A, > + (__v32hi) __C, (__v32hi) __D, > (__mmask32)__B); > +} > + > +extern __inline __m512i > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm512_maskz_shldv_epi16 (__mmask32 __A, __m512i __B, __m512i __C, > __m512i __D) > +{ > + return (__m512i)__builtin_ia32_vpshldv_v32hi_maskz ((__v32hi)__B, > + (__v32hi) __C, (__v32hi) __D, > (__mmask32)__A); > +} > + > #ifdef __DISABLE_AVX512VBMI2BW__ > #undef __DISABLE_AVX512VBMI2BW__ > > --- gcc/config/i386/avx512bitalgintrin.h.jj 2017-12-22 > 14:00:04.000000000 +0100 > +++ gcc/config/i386/avx512bitalgintrin.h 2017-12-22 > 17:39:52.615409924 +0100 > @@ -143,23 +143,6 @@ _mm256_maskz_popcnt_epi8 (__mmask32 __U, > _mm256_setzero_si256 (), > (__mmask32) __U); > } > -extern __inline __mmask16 > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm_bitshuffle_epi64_mask (__m128i __A, __m128i __B) > -{ > - return (__mmask16) __builtin_ia32_vpshufbitqmb128_mask ((__v2di) __A, > - (__v2di) __B, > - (__mmask16) -1); > -} > - > -extern __inline __mmask16 > -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > -_mm_mask_bitshuffle_epi64_mask (__mmask16 __M, __m128i __A, __m128i > __B) > -{ > - return (__mmask16) __builtin_ia32_vpshufbitqmb128_mask ((__v2di) __A, > - (__v2di) __B, > - (__mmask16) __M); > -} > > extern __inline __mmask32 > __attribute__((__gnu_inline__, __always_inline__, __artificial__)) > @@ -191,6 +174,24 @@ _mm256_mask_bitshuffle_epi64_mask (__mma > #define __DISABLE_AVX512BITALGVL__ > #endif /* __AVX512VLBW__ */ > > +extern __inline __mmask16 > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm_bitshuffle_epi64_mask (__m128i __A, __m128i __B) > +{ > + return (__mmask16) __builtin_ia32_vpshufbitqmb128_mask ((__v2di) __A, > + (__v2di) __B, > + (__mmask16) -1); > +} > + > +extern __inline __mmask16 > +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) > +_mm_mask_bitshuffle_epi64_mask (__mmask16 __M, __m128i __A, __m128i > __B) > +{ > + return (__mmask16) __builtin_ia32_vpshufbitqmb128_mask ((__v2di) __A, > + (__v2di) __B, > + (__mmask16) __M); > +} > + > extern __inline __m256i > __attribute__((__gnu_inline__, __always_inline__, __artificial__)) > _mm256_popcnt_epi8 (__m256i __A) > --- gcc/common/config/i386/i386-common.c.jj 2017-12-22 > 14:00:03.000000000 +0100 > +++ gcc/common/config/i386/i386-common.c 2017-12-22 > 15:09:07.875074385 +0100 > @@ -84,8 +84,10 @@ along with GCC; see the file COPYING3. > (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET) > #define OPTION_MASK_ISA_AVX512VNNI_SET \ > (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET) > -#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET > OPTION_MASK_ISA_AVX512VPOPCNTDQ > -#define OPTION_MASK_ISA_AVX512BITALG_SET > OPTION_MASK_ISA_AVX512BITALG > +#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \ > + (OPTION_MASK_ISA_AVX512VPOPCNTDQ | > OPTION_MASK_ISA_AVX512F_SET) > +#define OPTION_MASK_ISA_AVX512BITALG_SET \ > + (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET) > #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM > #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW > #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED > @@ -187,7 +189,8 @@ along with GCC; see the file COPYING3. > | OPTION_MASK_ISA_AVX512PF_UNSET | > OPTION_MASK_ISA_AVX512ER_UNSET \ > | OPTION_MASK_ISA_AVX512DQ_UNSET | > OPTION_MASK_ISA_AVX512BW_UNSET \ > | OPTION_MASK_ISA_AVX512VL_UNSET | > OPTION_MASK_ISA_AVX512VBMI2_UNSET \ > - | OPTION_MASK_ISA_AVX512VNNI_UNSET) > + | OPTION_MASK_ISA_AVX512VNNI_UNSET | > OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \ > + | OPTION_MASK_ISA_AVX512BITALG_UNSET) > #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD > #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF > #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER > @@ -257,6 +260,11 @@ along with GCC; see the file COPYING3. > (OPTION_MASK_ISA_MMX_UNSET \ > | OPTION_MASK_ISA_SSE_UNSET) > > +#define OPTION_MASK_ISA2_AVX512F_UNSET \ > + (OPTION_MASK_ISA_AVX5124FMAPS_UNSET | > OPTION_MASK_ISA_AVX5124VNNIW_UNSET) > +#define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ > + (OPTION_MASK_ISA2_AVX512F_UNSET | OPTION_MASK_ISA_MPX) > + > /* Implement TARGET_HANDLE_OPTION. */ > > bool > @@ -278,11 +286,11 @@ ix86_handle_option (struct gcc_options * > opts->x_ix86_isa_flags > &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET; > opts->x_ix86_isa_flags2 > - &= ~OPTION_MASK_ISA_MPX; > + &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET; > opts->x_ix86_isa_flags_explicit > |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET; > opts->x_ix86_isa_flags2_explicit > - |= OPTION_MASK_ISA_MPX; > + |= OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET; > > opts->x_target_flags &= ~MASK_80387; > } > @@ -339,6 +347,8 @@ ix86_handle_option (struct gcc_options * > { > opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET; > opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET; > + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; > + opts->x_ix86_isa_flags2_explicit |= > OPTION_MASK_ISA2_AVX512F_UNSET; > } > return true; > > @@ -352,6 +362,8 @@ ix86_handle_option (struct gcc_options * > { > opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET; > opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET; > + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; > + opts->x_ix86_isa_flags2_explicit |= > OPTION_MASK_ISA2_AVX512F_UNSET; > } > return true; > > @@ -365,6 +377,8 @@ ix86_handle_option (struct gcc_options * > { > opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET; > opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET; > + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; > + opts->x_ix86_isa_flags2_explicit |= > OPTION_MASK_ISA2_AVX512F_UNSET; > } > return true; > > @@ -378,6 +392,8 @@ ix86_handle_option (struct gcc_options * > { > opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET; > opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET; > + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; > + opts->x_ix86_isa_flags2_explicit |= > OPTION_MASK_ISA2_AVX512F_UNSET; > } > return true; > > @@ -391,6 +407,8 @@ ix86_handle_option (struct gcc_options * > { > opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET; > opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET; > + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; > + opts->x_ix86_isa_flags2_explicit |= > OPTION_MASK_ISA2_AVX512F_UNSET; > } > return true; > > @@ -404,6 +422,8 @@ ix86_handle_option (struct gcc_options * > { > opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET; > opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET; > + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; > + opts->x_ix86_isa_flags2_explicit |= > OPTION_MASK_ISA2_AVX512F_UNSET; > } > return true; > > @@ -417,6 +437,8 @@ ix86_handle_option (struct gcc_options * > { > opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET; > opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET; > + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; > + opts->x_ix86_isa_flags2_explicit |= > OPTION_MASK_ISA2_AVX512F_UNSET; > } > return true; > > @@ -430,6 +452,8 @@ ix86_handle_option (struct gcc_options * > { > opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET; > opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET; > + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; > + opts->x_ix86_isa_flags2_explicit |= > OPTION_MASK_ISA2_AVX512F_UNSET; > } > return true; > > @@ -443,20 +467,8 @@ ix86_handle_option (struct gcc_options * > { > opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET; > opts->x_ix86_isa_flags_explicit |= > OPTION_MASK_ISA_AVX512F_UNSET; > - > - /* Turn off additional isa flags. */ > - opts->x_ix86_isa_flags2 &= > ~OPTION_MASK_ISA_AVX5124FMAPS_UNSET; > - opts->x_ix86_isa_flags2_explicit > - |= OPTION_MASK_ISA_AVX5124FMAPS_UNSET; > - opts->x_ix86_isa_flags2 &= > ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET; > - opts->x_ix86_isa_flags2_explicit > - |= OPTION_MASK_ISA_AVX5124VNNIW_UNSET; > - opts->x_ix86_isa_flags2 &= > ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; > - opts->x_ix86_isa_flags2_explicit > - |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; > - opts->x_ix86_isa_flags2 &= > ~OPTION_MASK_ISA_AVX512BITALG_UNSET; > - opts->x_ix86_isa_flags2_explicit > - |= OPTION_MASK_ISA_AVX512BITALG_UNSET; > + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; > + opts->x_ix86_isa_flags2_explicit |= > OPTION_MASK_ISA2_AVX512F_UNSET; > } > return true; > > @@ -639,30 +651,28 @@ ix86_handle_option (struct gcc_options * > case OPT_mavx512vpopcntdq: > if (value) > { > - opts->x_ix86_isa_flags2 |= > OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET; > - opts->x_ix86_isa_flags2_explicit |= > OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET; > - opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; > - opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; > + opts->x_ix86_isa_flags |= > OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET; > + opts->x_ix86_isa_flags_explicit > + |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET; > } > else > { > - opts->x_ix86_isa_flags2 &= > ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; > - opts->x_ix86_isa_flags2_explicit |= > OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; > + opts->x_ix86_isa_flags &= > ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; > + opts->x_ix86_isa_flags_explicit > + |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; > } > return true; > > case OPT_mavx512bitalg: > if (value) > { > - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512BITALG_SET; > - opts->x_ix86_isa_flags2_explicit |= > OPTION_MASK_ISA_AVX512BITALG_SET; > - opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; > - opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; > + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET; > + opts->x_ix86_isa_flags_explicit |= > OPTION_MASK_ISA_AVX512BITALG_SET; > } > else > { > - opts->x_ix86_isa_flags2 &= > ~OPTION_MASK_ISA_AVX512BITALG_UNSET; > - opts->x_ix86_isa_flags2_explicit > + opts->x_ix86_isa_flags &= > ~OPTION_MASK_ISA_AVX512BITALG_UNSET; > + opts->x_ix86_isa_flags_explicit > |= OPTION_MASK_ISA_AVX512BITALG_UNSET; > } > return true; > @@ -779,6 +789,8 @@ ix86_handle_option (struct gcc_options * > case OPT_mno_sse4: > opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET; > opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET; > + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; > + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; > return true; > > case OPT_msse4a: > > > Jakub