James Greenhalgh <james.greenha...@arm.com> writes:
> On Sat, Jan 06, 2018 at 07:13:22PM +0000, Richard Sandiford wrote:
>> James Greenhalgh <james.greenha...@arm.com> writes:
>> > On Fri, Nov 03, 2017 at 05:50:54PM +0000, Richard Sandiford wrote:
>> >> This patch adds gcc.target/aarch64 tests for SVE, and forces some
>> >> existing Advanced SIMD tests to use -march=armv8-a.
>> >
>> > I'm going to assume that these new testcases are broadly sensible, and not
>> > spend any significant time looking at them.
>> >
>> > I'm not completely happy forcing the architecture to Armv8-a - it would be
>> > useful for our testing coverage if users which have configured with other
>> > architecture variants had this test execute in those environments. That
>> > way we'd check we still do the right thing once we have an implicit
>> > -march=armv8.2-a .
>> >
>> > However, as we don't have a good way to make that happen (other than maybe
>> > only forcing the arch if we are in a configuration wired for SVE?) I'm
>> > happy with this patch as a compromise for now.
>>
>> Would something like LLVM's -mattr be useful? Then we could have
>> -mattr=+nosve without having to change the base architecture.
>>
>> I suppose we'd need to be careful about how it interacts with -march
>> though, so it probably isn't GCC 8 material. I'll try only forcing
>> the arch when we're compiling for SVE, like you say.
>
> (Sorry if you took a duplicate of this - I mistakenly sent with a disclaimer)
>
> We also could do this with Target pragmas:
>
> #pragma GCC target ("+nosve")
>
> Should work here I think.
Yeah, it does, thanks. I switched to that instead of forcing -march=.
>> Not strictly related, but do you think it's OK to require binutils 2.28+
>> when testing GCC (rather than simply building it)? When trying with an
>> older OS the other day, I realised that the SVE dg-do assemble tests
>> would fail for 2.27 and earlier. We'd need something like:
>>
>> /* { dg-do assemble { aarch64_sve_asm } } */
>>
>> if we wanted to support older binutils.
>
> Personally I think this is OK. We have the same problem with other
> new instructions we add and want assemble tests for.
I later saw that we have aarch64_asm_<foo>_ok, so I added "sve" to the
list and used it to protect dg-do assemble tests.
In another message you said:
> Additionally, I'd be happy with the whole AArch64 testsuite being organised
> in to folders (doing this might also make it easier for us to turn all SVE
> tests off with older assemblers, by using the skipping the exp file if we
> can't find support).
I agree organising it into directories is nicer, and it means that we
can add the -march= option in the harness rather than each individual
dg-options line. That in turn makes it easy to avoid overriding -march=
if the setting that the tester chose (or the toolchain's default setting)
already includes SVE.
Here's what I plan to commit (without reposting the new tests).
Thanks,
Richard
2018-01-12 Richard Sandiford <richard.sandif...@linaro.org>
Alan Hayward <alan.hayw...@arm.com>
David Sherwood <david.sherw...@arm.com>
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_aarch64_asm_sve_ok):
New proc.
* gcc.target/aarch64/bic_imm_1.c: Use #pragma GCC target "+nosve".
* gcc.target/aarch64/fmaxmin.c: Likewise.
* gcc.target/aarch64/fmul_fcvt_2.c: Likewise.
* gcc.target/aarch64/orr_imm_1.c: Likewise.
* gcc.target/aarch64/pr62178.c: Likewise.
* gcc.target/aarch64/pr71727-2.c: Likewise.
* gcc.target/aarch64/saddw-1.c: Likewise.
* gcc.target/aarch64/saddw-2.c: Likewise.
* gcc.target/aarch64/uaddw-1.c: Likewise.
* gcc.target/aarch64/uaddw-2.c: Likewise.
* gcc.target/aarch64/uaddw-3.c: Likewise.
* gcc.target/aarch64/vect-add-sub-cond.c: Likewise.
* gcc.target/aarch64/vect-compile.c: Likewise.
* gcc.target/aarch64/vect-faddv-compile.c: Likewise.
* gcc.target/aarch64/vect-fcm-eq-d.c: Likewise.
* gcc.target/aarch64/vect-fcm-eq-f.c: Likewise.
* gcc.target/aarch64/vect-fcm-ge-d.c: Likewise.
* gcc.target/aarch64/vect-fcm-ge-f.c: Likewise.
* gcc.target/aarch64/vect-fcm-gt-d.c: Likewise.
* gcc.target/aarch64/vect-fcm-gt-f.c: Likewise.
* gcc.target/aarch64/vect-fmax-fmin-compile.c: Likewise.
* gcc.target/aarch64/vect-fmaxv-fminv-compile.c: Likewise.
* gcc.target/aarch64/vect-fmovd-zero.c: Likewise.
* gcc.target/aarch64/vect-fmovd.c: Likewise.
* gcc.target/aarch64/vect-fmovf-zero.c: Likewise.
* gcc.target/aarch64/vect-fmovf.c: Likewise.
* gcc.target/aarch64/vect-fp-compile.c: Likewise.
* gcc.target/aarch64/vect-ld1r-compile-fp.c: Likewise.
* gcc.target/aarch64/vect-ld1r-compile.c: Likewise.
* gcc.target/aarch64/vect-movi.c: Likewise.
* gcc.target/aarch64/vect-mull-compile.c: Likewise.
* gcc.target/aarch64/vect-reduc-or_1.c: Likewise.
* gcc.target/aarch64/vect-vaddv.c: Likewise.
* gcc.target/aarch64/vect_saddl_1.c: Likewise.
* gcc.target/aarch64/vect_smlal_1.c: Likewise.
* gcc.target/aarch64/vector_initialization_nostack.c: XFAIL for
fixed-length SVE.
* gcc.target/aarch64/sve/aarch64-sve.exp: New file.
* gcc.target/aarch64/sve/arith_1.c: New test.
* gcc.target/aarch64/sve/const_pred_1.C: Likewise.
* gcc.target/aarch64/sve/const_pred_2.C: Likewise.
* gcc.target/aarch64/sve/const_pred_3.C: Likewise.
* gcc.target/aarch64/sve/const_pred_4.C: Likewise.
* gcc.target/aarch64/sve/cvtf_signed_1.c: Likewise.
* gcc.target/aarch64/sve/cvtf_signed_1_run.c: Likewise.
* gcc.target/aarch64/sve/cvtf_unsigned_1.c: Likewise.
* gcc.target/aarch64/sve/cvtf_unsigned_1_run.c: Likewise.
* gcc.target/aarch64/sve/dup_imm_1.c: Likewise.
* gcc.target/aarch64/sve/dup_imm_1_run.c: Likewise.
* gcc.target/aarch64/sve/dup_lane_1.c: Likewise.
* gcc.target/aarch64/sve/ext_1.c: Likewise.
* gcc.target/aarch64/sve/ext_2.c: Likewise.
* gcc.target/aarch64/sve/extract_1.c: Likewise.
* gcc.target/aarch64/sve/extract_2.c: Likewise.
* gcc.target/aarch64/sve/extract_3.c: Likewise.
* gcc.target/aarch64/sve/extract_4.c: Likewise.
* gcc.target/aarch64/sve/fabs_1.c: Likewise.
* gcc.target/aarch64/sve/fcvtz_signed_1.c: Likewise.
* gcc.target/aarch64/sve/fcvtz_signed_1_run.c: Likewise.
* gcc.target/aarch64/sve/fcvtz_unsigned_1.c: Likewise.
* gcc.target/aarch64/sve/fcvtz_unsigned_1_run.c: Likewise.
* gcc.target/aarch64/sve/fdiv_1.c: Likewise.
* gcc.target/aarch64/sve/fdup_1.c: Likewise.
* gcc.target/aarch64/sve/fdup_1_run.c: Likewise.
* gcc.target/aarch64/sve/fmad_1.c: Likewise.
* gcc.target/aarch64/sve/fmla_1.c: Likewise.
* gcc.target/aarch64/sve/fmls_1.c: Likewise.
* gcc.target/aarch64/sve/fmsb_1.c: Likewise.
* gcc.target/aarch64/sve/fmul_1.c: Likewise.
* gcc.target/aarch64/sve/fneg_1.c: Likewise.
* gcc.target/aarch64/sve/fnmad_1.c: Likewise.
* gcc.target/aarch64/sve/fnmla_1.c: Likewise.
* gcc.target/aarch64/sve/fnmls_1.c: Likewise.
* gcc.target/aarch64/sve/fnmsb_1.c: Likewise.
* gcc.target/aarch64/sve/fp_arith_1.c: Likewise.
* gcc.target/aarch64/sve/frinta_1.c: Likewise.
* gcc.target/aarch64/sve/frinti_1.c: Likewise.
* gcc.target/aarch64/sve/frintm_1.c: Likewise.
* gcc.target/aarch64/sve/frintp_1.c: Likewise.
* gcc.target/aarch64/sve/frintx_1.c: Likewise.
* gcc.target/aarch64/sve/frintz_1.c: Likewise.
* gcc.target/aarch64/sve/fsqrt_1.c: Likewise.
* gcc.target/aarch64/sve/fsubr_1.c: Likewise.
* gcc.target/aarch64/sve/index_1.c: Likewise.
* gcc.target/aarch64/sve/index_1_run.c: Likewise.
* gcc.target/aarch64/sve/ld1r_1.c: Likewise.
* gcc.target/aarch64/sve/load_const_offset_1.c: Likewise.
* gcc.target/aarch64/sve/load_const_offset_2.c: Likewise.
* gcc.target/aarch64/sve/load_const_offset_3.c: Likewise.
* gcc.target/aarch64/sve/load_scalar_offset_1.c: Likewise.
* gcc.target/aarch64/sve/logical_1.c: Likewise.
* gcc.target/aarch64/sve/loop_add_1.c: Likewise.
* gcc.target/aarch64/sve/loop_add_1_run.c: Likewise.
* gcc.target/aarch64/sve/mad_1.c: Likewise.
* gcc.target/aarch64/sve/maxmin_1.c: Likewise.
* gcc.target/aarch64/sve/maxmin_1_run.c: Likewise.
* gcc.target/aarch64/sve/maxmin_strict_1.c: Likewise.
* gcc.target/aarch64/sve/maxmin_strict_1_run.c: Likewise.
* gcc.target/aarch64/sve/mla_1.c: Likewise.
* gcc.target/aarch64/sve/mls_1.c: Likewise.
* gcc.target/aarch64/sve/mov_rr_1.c: Likewise.
* gcc.target/aarch64/sve/msb_1.c: Likewise.
* gcc.target/aarch64/sve/mul_1.c: Likewise.
* gcc.target/aarch64/sve/neg_1.c: Likewise.
* gcc.target/aarch64/sve/nlogical_1.c: Likewise.
* gcc.target/aarch64/sve/nlogical_1_run.c: Likewise.
* gcc.target/aarch64/sve/pack_1.c: Likewise.
* gcc.target/aarch64/sve/pack_1_run.c: Likewise.
* gcc.target/aarch64/sve/pack_fcvt_signed_1.c: Likewise.
* gcc.target/aarch64/sve/pack_fcvt_signed_1_run.c: Likewise.
* gcc.target/aarch64/sve/pack_fcvt_unsigned_1.c: Likewise.
* gcc.target/aarch64/sve/pack_fcvt_unsigned_1_run.c: Likewise.
* gcc.target/aarch64/sve/pack_float_1.c: Likewise.
* gcc.target/aarch64/sve/pack_float_1_run.c: Likewise.
* gcc.target/aarch64/sve/popcount_1.c: Likewise.
* gcc.target/aarch64/sve/popcount_1_run.c: Likewise.
* gcc.target/aarch64/sve/reduc_1.c: Likewise.
* gcc.target/aarch64/sve/reduc_1_run.c: Likewise.
* gcc.target/aarch64/sve/reduc_2.c: Likewise.
* gcc.target/aarch64/sve/reduc_2_run.c: Likewise.
* gcc.target/aarch64/sve/reduc_3.c: Likewise.
* gcc.target/aarch64/sve/rev_1.c: Likewise.
* gcc.target/aarch64/sve/revb_1.c: Likewise.
* gcc.target/aarch64/sve/revh_1.c: Likewise.
* gcc.target/aarch64/sve/revw_1.c: Likewise.
* gcc.target/aarch64/sve/shift_1.c: Likewise.
* gcc.target/aarch64/sve/single_1.c: Likewise.
* gcc.target/aarch64/sve/single_2.c: Likewise.
* gcc.target/aarch64/sve/single_3.c: Likewise.
* gcc.target/aarch64/sve/single_4.c: Likewise.
* gcc.target/aarch64/sve/spill_1.c: Likewise.
* gcc.target/aarch64/sve/store_scalar_offset_1.c: Likewise.
* gcc.target/aarch64/sve/subr_1.c: Likewise.
* gcc.target/aarch64/sve/trn1_1.c: Likewise.
* gcc.target/aarch64/sve/trn2_1.c: Likewise.
* gcc.target/aarch64/sve/unpack_fcvt_signed_1.c: Likewise.
* gcc.target/aarch64/sve/unpack_fcvt_signed_1_run.c: Likewise.
* gcc.target/aarch64/sve/unpack_fcvt_unsigned_1.c: Likewise.
* gcc.target/aarch64/sve/unpack_fcvt_unsigned_1_run.c: Likewise.
* gcc.target/aarch64/sve/unpack_float_1.c: Likewise.
* gcc.target/aarch64/sve/unpack_float_1_run.c: Likewise.
* gcc.target/aarch64/sve/unpack_signed_1.c: Likewise.
* gcc.target/aarch64/sve/unpack_signed_1_run.c: Likewise.
* gcc.target/aarch64/sve/unpack_unsigned_1.c: Likewise.
* gcc.target/aarch64/sve/unpack_unsigned_1_run.c: Likewise.
* gcc.target/aarch64/sve/uzp1_1.c: Likewise.
* gcc.target/aarch64/sve/uzp1_1_run.c: Likewise.
* gcc.target/aarch64/sve/uzp2_1.c: Likewise.
* gcc.target/aarch64/sve/uzp2_1_run.c: Likewise.
* gcc.target/aarch64/sve/vcond_1.C: Likewise.
* gcc.target/aarch64/sve/vcond_1_run.C: Likewise.
* gcc.target/aarch64/sve/vcond_2.c: Likewise.
* gcc.target/aarch64/sve/vcond_2_run.c: Likewise.
* gcc.target/aarch64/sve/vcond_3.c: Likewise.
* gcc.target/aarch64/sve/vcond_4.c: Likewise.
* gcc.target/aarch64/sve/vcond_4_run.c: Likewise.
* gcc.target/aarch64/sve/vcond_5.c: Likewise.
* gcc.target/aarch64/sve/vcond_5_run.c: Likewise.
* gcc.target/aarch64/sve/vcond_6.c: Likewise.
* gcc.target/aarch64/sve/vcond_6_run.c: Likewise.
* gcc.target/aarch64/sve/vec_init_1.c: Likewise.
* gcc.target/aarch64/sve/vec_init_1_run.c: Likewise.
* gcc.target/aarch64/sve/vec_init_2.c: Likewise.
* gcc.target/aarch64/sve/vec_perm_1.c: Likewise.
* gcc.target/aarch64/sve/vec_perm_1_run.c: Likewise.
* gcc.target/aarch64/sve/vec_perm_1_overrange_run.c: Likewise.
* gcc.target/aarch64/sve/vec_perm_const_1.c: Likewise.
* gcc.target/aarch64/sve/vec_perm_const_1_overrun.c: Likewise.
* gcc.target/aarch64/sve/vec_perm_const_1_run.c: Likewise.
* gcc.target/aarch64/sve/vec_perm_const_single_1.c: Likewise.
* gcc.target/aarch64/sve/vec_perm_const_single_1_run.c: Likewise.
* gcc.target/aarch64/sve/vec_perm_single_1.c: Likewise.
* gcc.target/aarch64/sve/vec_perm_single_1_run.c: Likewise.
* gcc.target/aarch64/sve/zip1_1.c: Likewise.
* gcc.target/aarch64/sve/zip2_1.c: Likewise.
Index: gcc/testsuite/lib/target-supports.exp
===================================================================
--- gcc/testsuite/lib/target-supports.exp 2018-01-12 15:13:42.557888273
+0000
+++ gcc/testsuite/lib/target-supports.exp 2018-01-12 15:13:44.050826874
+0000
@@ -8590,7 +8590,7 @@ proc check_effective_target_aarch64_tiny
# Create functions to check that the AArch64 assembler supports the
# various architecture extensions via the .arch_extension pseudo-op.
-foreach { aarch64_ext } { "fp" "simd" "crypto" "crc" "lse" "dotprod"} {
+foreach { aarch64_ext } { "fp" "simd" "crypto" "crc" "lse" "dotprod" "sve"} {
eval [string map [list FUNC $aarch64_ext] {
proc check_effective_target_aarch64_asm_FUNC_ok { } {
if { [istarget aarch64*-*-*] } {
Index: gcc/testsuite/gcc.target/aarch64/bic_imm_1.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/bic_imm_1.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/bic_imm_1.c 2018-01-12
15:13:44.034827531 +0000
@@ -1,6 +1,8 @@
/* { dg-do assemble } */
/* { dg-options "-O2 --save-temps -ftree-vectorize" } */
+#pragma GCC target "+nosve"
+
/* Each function uses the correspoding 'CLASS' in
Marco CHECK (aarch64_simd_valid_immediate). */
Index: gcc/testsuite/gcc.target/aarch64/fmaxmin.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/fmaxmin.c 2018-01-12 15:13:42.557888273
+0000
+++ gcc/testsuite/gcc.target/aarch64/fmaxmin.c 2018-01-12 15:13:44.034827531
+0000
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-options "-O2 -ftree-vectorize -fno-inline -fno-vect-cost-model
-save-temps" } */
+#pragma GCC target "+nosve"
extern void abort (void);
double fmax (double, double);
Index: gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c 2018-01-12
15:13:44.034827531 +0000
@@ -1,6 +1,8 @@
/* { dg-do run } */
/* { dg-options "-save-temps -O2 -ftree-vectorize -fno-inline
-fno-vect-cost-model" } */
+#pragma GCC target "+nosve"
+
#define N 1024
#define FUNC_DEF(__a) \
Index: gcc/testsuite/gcc.target/aarch64/orr_imm_1.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/orr_imm_1.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/orr_imm_1.c 2018-01-12
15:13:44.034827531 +0000
@@ -1,6 +1,8 @@
/* { dg-do assemble } */
/* { dg-options "-O2 --save-temps -ftree-vectorize" } */
+#pragma GCC target "+nosve"
+
/* Each function uses the correspoding 'CLASS' in
Marco CHECK (aarch64_simd_valid_immediate). */
Index: gcc/testsuite/gcc.target/aarch64/pr62178.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/pr62178.c 2018-01-12 15:13:42.557888273
+0000
+++ gcc/testsuite/gcc.target/aarch64/pr62178.c 2018-01-12 15:13:44.034827531
+0000
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O3" } */
+#pragma GCC target "+nosve"
+
int a[30 +1][30 +1], b[30 +1][30 +1], r[30 +1][30 +1];
void foo (void) {
Index: gcc/testsuite/gcc.target/aarch64/pr71727-2.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/pr71727-2.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/pr71727-2.c 2018-01-12
15:13:44.034827531 +0000
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-mstrict-align -O3" } */
+#pragma GCC target "+nosve"
+
unsigned char foo(const unsigned char *buffer, unsigned int length)
{
unsigned char sum;
Index: gcc/testsuite/gcc.target/aarch64/saddw-1.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/saddw-1.c 2018-01-12 15:13:42.557888273
+0000
+++ gcc/testsuite/gcc.target/aarch64/saddw-1.c 2018-01-12 15:13:44.034827531
+0000
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O3" } */
+#pragma GCC target "+nosve"
+
int
t6(int len, void * dummy, short * __restrict x)
{
Index: gcc/testsuite/gcc.target/aarch64/saddw-2.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/saddw-2.c 2018-01-12 15:13:42.557888273
+0000
+++ gcc/testsuite/gcc.target/aarch64/saddw-2.c 2018-01-12 15:13:44.034827531
+0000
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O3" } */
+#pragma GCC target "+nosve"
+
int
t6(int len, void * dummy, int * __restrict x)
{
Index: gcc/testsuite/gcc.target/aarch64/uaddw-1.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/uaddw-1.c 2018-01-12 15:13:42.557888273
+0000
+++ gcc/testsuite/gcc.target/aarch64/uaddw-1.c 2018-01-12 15:13:44.049826915
+0000
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O3" } */
+#pragma GCC target "+nosve"
+
int
t6(int len, void * dummy, unsigned short * __restrict x)
{
Index: gcc/testsuite/gcc.target/aarch64/uaddw-2.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/uaddw-2.c 2018-01-12 15:13:42.557888273
+0000
+++ gcc/testsuite/gcc.target/aarch64/uaddw-2.c 2018-01-12 15:13:44.049826915
+0000
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O3" } */
+#pragma GCC target "+nosve"
+
int
t6(int len, void * dummy, unsigned short * __restrict x)
{
Index: gcc/testsuite/gcc.target/aarch64/uaddw-3.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/uaddw-3.c 2018-01-12 15:13:42.557888273
+0000
+++ gcc/testsuite/gcc.target/aarch64/uaddw-3.c 2018-01-12 15:13:44.049826915
+0000
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O3" } */
+#pragma GCC target "+nosve"
+
int
t6(int len, void * dummy, char * __restrict x)
{
Index: gcc/testsuite/gcc.target/aarch64/vect-add-sub-cond.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-add-sub-cond.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-add-sub-cond.c 2018-01-12
15:13:44.049826915 +0000
@@ -3,6 +3,8 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize" } */
+#pragma GCC target "+nosve"
+
#define COUNT1(X) if (X) count += 1
#define COUNT2(X) if (X) count -= 1
#define COUNT3(X) count += (X)
Index: gcc/testsuite/gcc.target/aarch64/vect-compile.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-compile.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-compile.c 2018-01-12
15:13:44.049826915 +0000
@@ -1,7 +1,8 @@
-
/* { dg-do compile } */
/* { dg-options "-O3" } */
+#pragma GCC target "+nosve"
+
#include "vect.x"
/* { dg-final { scan-assembler "orn\\tv" } } */
Index: gcc/testsuite/gcc.target/aarch64/vect-faddv-compile.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-faddv-compile.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-faddv-compile.c 2018-01-12
15:13:44.049826915 +0000
@@ -1,7 +1,8 @@
-
/* { dg-do compile } */
/* { dg-options "-O3 -ffast-math" } */
+#pragma GCC target "+nosve"
+
#include "vect-faddv.x"
/* { dg-final { scan-assembler-times "faddp\\tv" 2} } */
Index: gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c 2018-01-12
15:13:44.049826915 +0000
@@ -1,6 +1,8 @@
/* { dg-do run } */
/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops
--save-temps -fno-inline -fno-vect-cost-model" } */
+#pragma GCC target "+nosve"
+
#define FTYPE double
#define ITYPE long
#define OP ==
Index: gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c 2018-01-12
15:13:44.049826915 +0000
@@ -1,6 +1,8 @@
/* { dg-do run } */
/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops
--save-temps -fno-inline" } */
+#pragma GCC target "+nosve"
+
#define FTYPE float
#define ITYPE int
#define OP ==
Index: gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c 2018-01-12
15:13:44.049826915 +0000
@@ -1,6 +1,8 @@
/* { dg-do run } */
/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops
--save-temps -fno-inline -fno-vect-cost-model" } */
+#pragma GCC target "+nosve"
+
#define FTYPE double
#define ITYPE long
#define OP >=
Index: gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c 2018-01-12
15:13:44.049826915 +0000
@@ -1,6 +1,8 @@
/* { dg-do run } */
/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops
--save-temps -fno-inline" } */
+#pragma GCC target "+nosve"
+
#define FTYPE float
#define ITYPE int
#define OP >=
Index: gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c 2018-01-12
15:13:44.049826915 +0000
@@ -1,6 +1,8 @@
/* { dg-do run } */
/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops
--save-temps -fno-inline -fno-vect-cost-model" } */
+#pragma GCC target "+nosve"
+
#define FTYPE double
#define ITYPE long
#define OP >
Index: gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c 2018-01-12
15:13:44.049826915 +0000
@@ -1,6 +1,8 @@
/* { dg-do run } */
/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops
--save-temps -fno-inline" } */
+#pragma GCC target "+nosve"
+
#define FTYPE float
#define ITYPE int
#define OP >
Index: gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin-compile.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin-compile.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin-compile.c 2018-01-12
15:13:44.049826915 +0000
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O3 -ffast-math" } */
+#pragma GCC target "+nosve"
+
#include "vect-fmax-fmin.x"
/* { dg-final { scan-assembler "fmaxnm\\tv" } } */
Index: gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv-compile.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv-compile.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv-compile.c 2018-01-12
15:13:44.050826874 +0000
@@ -1,7 +1,8 @@
-
/* { dg-do compile } */
/* { dg-options "-O3 -ffast-math -fno-vect-cost-model" } */
+#pragma GCC target "+nosve"
+
#include "vect-fmaxv-fminv.x"
/* { dg-final { scan-assembler "fminnmv" } } */
Index: gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c 2018-01-12
15:13:44.050826874 +0000
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all
-fno-vect-cost-model" } */
+#pragma GCC target "+nosve"
+
#define N 32
void
Index: gcc/testsuite/gcc.target/aarch64/vect-fmovd.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-fmovd.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-fmovd.c 2018-01-12
15:13:44.050826874 +0000
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all
-fno-vect-cost-model" } */
+#pragma GCC target "+nosve"
+
#define N 32
void
Index: gcc/testsuite/gcc.target/aarch64/vect-fmovf-zero.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-fmovf-zero.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-fmovf-zero.c 2018-01-12
15:13:44.050826874 +0000
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all
-fno-vect-cost-model" } */
+#pragma GCC target "+nosve"
+
#define N 32
void
Index: gcc/testsuite/gcc.target/aarch64/vect-fmovf.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-fmovf.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-fmovf.c 2018-01-12
15:13:44.050826874 +0000
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all
-fno-vect-cost-model" } */
+#pragma GCC target "+nosve"
+
#define N 32
void
Index: gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c 2018-01-12
15:13:44.050826874 +0000
@@ -1,8 +1,8 @@
-
-
/* { dg-do compile } */
/* { dg-options "-O3" } */
+#pragma GCC target "+nosve"
+
#include "vect-fp.x"
/* { dg-final { scan-assembler "fadd\\tv" } } */
Index: gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c 2018-01-12
15:13:44.050826874 +0000
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O3 -fno-vect-cost-model" } */
+#pragma GCC target "+nosve"
+
#include "stdint.h"
#include "vect-ld1r.x"
Index: gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c 2018-01-12
15:13:44.050826874 +0000
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O3 -fno-vect-cost-model" } */
+#pragma GCC target "+nosve"
+
#include "stdint.h"
#include "vect-ld1r.x"
Index: gcc/testsuite/gcc.target/aarch64/vect-movi.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-movi.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-movi.c 2018-01-12
15:13:44.050826874 +0000
@@ -1,6 +1,8 @@
/* { dg-do run } */
/* { dg-options "-O3 --save-temps -fno-inline" } */
+#pragma GCC target "+nosve"
+
extern void abort (void);
#define N 16
Index: gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c 2018-01-12
15:13:44.050826874 +0000
@@ -1,7 +1,8 @@
-
/* { dg-do compile } */
/* { dg-options "-O3" } */
+#pragma GCC target "+nosve"
+
#define N 16
#include "vect-mull.x"
Index: gcc/testsuite/gcc.target/aarch64/vect-reduc-or_1.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-reduc-or_1.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-reduc-or_1.c 2018-01-12
15:13:44.050826874 +0000
@@ -2,6 +2,8 @@
/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all
-fno-vect-cost-model" } */
/* Write a reduction loop to be reduced using whole vector right shift. */
+#pragma GCC target "+nosve"
+
extern void abort (void);
unsigned char in[8] __attribute__((__aligned__(16)));
Index: gcc/testsuite/gcc.target/aarch64/vect-vaddv.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect-vaddv.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect-vaddv.c 2018-01-12
15:13:44.050826874 +0000
@@ -1,6 +1,8 @@
/* { dg-do run } */
/* { dg-options "-O3 --save-temps -ffast-math" } */
+#pragma GCC target "+nosve"
+
#include <arm_neon.h>
extern void abort (void);
Index: gcc/testsuite/gcc.target/aarch64/vect_saddl_1.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect_saddl_1.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect_saddl_1.c 2018-01-12
15:13:44.050826874 +0000
@@ -1,6 +1,8 @@
/* { dg-do run } */
/* { dg-options "-O3 -fno-inline -save-temps -fno-vect-cost-model
-fno-ipa-icf" } */
+#pragma GCC target "+nosve"
+
typedef signed char S8_t;
typedef signed short S16_t;
typedef signed int S32_t;
Index: gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c 2018-01-12
15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c 2018-01-12
15:13:44.050826874 +0000
@@ -1,6 +1,8 @@
/* { dg-do run } */
/* { dg-options "-O3 -fno-inline -save-temps -fno-vect-cost-model
-fno-ipa-icf" } */
+#pragma GCC target "+nosve"
+
typedef signed char S8_t;
typedef signed short S16_t;
typedef signed int S32_t;
Index: gcc/testsuite/gcc.target/aarch64/vector_initialization_nostack.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/vector_initialization_nostack.c
2018-01-12 15:13:42.557888273 +0000
+++ gcc/testsuite/gcc.target/aarch64/vector_initialization_nostack.c
2018-01-12 15:13:44.050826874 +0000
@@ -49,5 +49,6 @@ f12 (void)
return sum;
}
-
-/* { dg-final { scan-assembler-not "sp" } } */
+/* Fails for fixed-length SVE because we lack a vec_init pattern.
+ A later patch fixes this in generic code. */
+/* { dg-final { scan-assembler-not "sp" { xfail { aarch64_sve && { !
vect_variable_length } } } } } */
Index: gcc/testsuite/gcc.target/aarch64/sve/aarch64-sve.exp
===================================================================
--- /dev/null 2018-01-12 06:40:27.684409621 +0000
+++ gcc/testsuite/gcc.target/aarch64/sve/aarch64-sve.exp 2018-01-12
15:13:44.035827490 +0000
@@ -0,0 +1,52 @@
+# Specific regression driver for AArch64 SVE.
+# Copyright (C) 2009-2018 Free Software Foundation, Inc.
+# Contributed by ARM Ltd.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>. */
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an AArch64 target.
+if {![istarget aarch64*-*-*] } then {
+ return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+ set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Force SVE if we're not testing it already.
+if { [check_effective_target_aarch64_sve] } {
+ set sve_flags ""
+} else {
+ set sve_flags "-march=armv8.2-a+sve"
+}
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+ $sve_flags $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
