On Tue, Jan 23, 2018 at 02:49:03PM +0000, Kyrill Tkachov wrote: > Hi all, > > This patch fixes the testsuite failures gcc.target/aarch64/subs_compare_1.c > and subs_compare_2.c The tests check that we combine a sequence like: > sub w2, w0, w1 > cmp w0, w1 > > into > subs w2, w0, w1 > > This is done by a couple of peepholes in aarch64.md. > > Unfortunately due to scheduling and other optimisations the SUB and CMP > can come in a different order: > cmp w0, w1 > sub w0, w0, w1 > > And the existing peepholes cannot catch that and we fail to combine the two. > This patch adds a peephole that matches the CMP as the first insn and the SUB > as the second and outputs a SUBS. This is almost equivalent to the existing > peephole that matches SUB first and CMP second except that it doesn't have > the restriction that the output register of the SUB has to not be one of the > input registers. Remember "sub w0, w0, w1 ; cmp w0, w1" is *not* equivalent > to: "subs w0, w0, w1" but "cmp w0, w1 ; sub w0, w0, w1" is. > > So this is what this patch does. It adds a peephole for the case above and > one for the SUB-immediate variant (because the SUB-immediate is represented > as PLUS-of-negated-immediate and thus has different RTL structure). > > Bootstrapped and tested on aarch64-none-linux-gnu. > > Ok for trunk?
OK. Thanks, James > Thanks, > Kyrill > > 2018-01-23 Kyrylo Tkachov <kyrylo.tkac...@arm.com> > > * config/aarch64/aarch64.md: Add peepholes for CMP + SUB -> SUBS > and CMP + SUB-immediate -> SUBS.
