Patches #5..8 just add comments and reformat movd{f,d} constraints and
attributes so that it is a lot easier to tell which constraints and attributes
go together. These do not (or at least should not) change the code generated.
Patch #9 does the same thing for mov{sf,sd} when floating point registers are
not available.
I have done both big and little endian bootstrap builds with all 5 patches
installed. There were no regressions.
2018-03-22 Michael Meissner <meiss...@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (mov<mode>_softfloat, FMOVE32):
Reformat alternatives and attributes so it is easier to identify
which constraints/attributes go with which instruction.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 258737)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -7217,9 +7217,17 @@ (define_insn "movsd_hardfloat"
"load, fpload, store, fpstore, mffgpr, mftgpr,
fpsimple, *, mtjmpr, mfjmpr, *")])
+;; MR MT%0 MF%0 LWZ STW LI
+;; LIS G-const. F/n-const NOP
(define_insn "*mov<mode>_softfloat"
- [(set (match_operand:FMOVE32 0 "nonimmediate_operand"
"=r,cl,r,r,m,r,r,r,r,*h")
- (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
+ [(set (match_operand:FMOVE32 0 "nonimmediate_operand"
+ "=r, cl, r, r, m, r,
+ r, r, r, *h")
+
+ (match_operand:FMOVE32 1 "input_operand"
+ "r, r, h, m, r, I,
+ L, G, Fn, 0"))]
+
"(gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))
&& TARGET_SOFT_FLOAT"
@@ -7234,8 +7242,13 @@ (define_insn "*mov<mode>_softfloat"
#
#
nop"
- [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
- (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
+ [(set_attr "type"
+ "*, mtjmpr, mfjmpr, load, store, *,
+ *, *, *, *")
+
+ (set_attr "length"
+ "4, 4, 4, 4, 4, 4,
+ 4, 4, 8, 4")])
;; Like movsf, but adjust a SI value to be used in a SF context, i.e.
;; (set (reg:SF ...) (subreg:SF (reg:SI ...) 0))
