From: Claudiu Zissulescu <claz...@gmail.com>
Allow signed 6-bit short immediates into st[d] instructions.
2017-10-19 Claudiu Zissulescu <claz...@synopsys.com>
* config/arc/arc.c (arc_split_move): Allow signed 6-bit constants
as source of std instructions.
* config/arc/arc.md (movsi_insn): Update pattern predicate to
allow 6-bit constants as source for store instructions.
(movdi_insn): Update instruction pattern to allow 6-bit constants
as source for store instructions.
testsuite/
2017-10-19 Claudiu Zissulescu <claz...@synopsys.com>
* gcc.target/arc/store-merge-1.c: New test.
* gcc.target/arc/add_n-combine.c: Update test.
---
gcc/config/arc/arc.c | 3 ++-
gcc/config/arc/arc.md | 25 +++++++++++++------------
gcc/testsuite/gcc.target/arc/add_n-combine.c | 2 +-
gcc/testsuite/gcc.target/arc/store-merge-1.c | 17 +++++++++++++++++
4 files changed, 33 insertions(+), 14 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arc/store-merge-1.c
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 47d3ba4..2ccdce8 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -9669,7 +9669,8 @@ arc_split_move (rtx *operands)
if (TARGET_LL64
&& ((memory_operand (operands[0], mode)
- && even_register_operand (operands[1], mode))
+ && (even_register_operand (operands[1], mode)
+ || satisfies_constraint_Cm3 (operands[1])))
|| (memory_operand (operands[1], mode)
&& even_register_operand (operands[0], mode))))
{
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index ffd9d5b..0fc7aba 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -740,7 +740,9 @@ archs4x, archs4xd, archs4xd_slow"
/* Don't use a LIMM that we could load with a single insn - we loose
delay-slot filling opportunities. */
&& !satisfies_constraint_I (operands[1])
- && satisfies_constraint_Usc (operands[0]))"
+ && satisfies_constraint_Usc (operands[0]))
+ || (satisfies_constraint_Cm3 (operands[1])
+ && memory_operand (operands[0], SImode))"
"@
mov%? %0,%1%& ;0
mov%? %0,%1%& ;1
@@ -1237,10 +1239,12 @@ archs4x, archs4xd, archs4xd_slow"
")
(define_insn_and_split "*movdi_insn"
- [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r,m")
- (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,c"))]
+ [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r, m")
+ (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,cCm3"))]
"register_operand (operands[0], DImode)
- || register_operand (operands[1], DImode)"
+ || register_operand (operands[1], DImode)
+ || (satisfies_constraint_Cm3 (operands[1])
+ && memory_operand (operands[0], DImode))"
"*
{
switch (which_alternative)
@@ -1250,19 +1254,16 @@ archs4x, archs4xd, archs4xd_slow"
case 2:
if (TARGET_LL64
- && ((even_register_operand (operands[0], DImode)
- && memory_operand (operands[1], DImode))
- || (memory_operand (operands[0], DImode)
- && even_register_operand (operands[1], DImode))))
+ && memory_operand (operands[1], DImode)
+ && even_register_operand (operands[0], DImode))
return \"ldd%U1%V1 %0,%1%&\";
return \"#\";
case 3:
if (TARGET_LL64
- && ((even_register_operand (operands[0], DImode)
- && memory_operand (operands[1], DImode))
- || (memory_operand (operands[0], DImode)
- && even_register_operand (operands[1], DImode))))
+ && memory_operand (operands[0], DImode)
+ && (even_register_operand (operands[1], DImode)
+ || satisfies_constraint_Cm3 (operands[1])))
return \"std%U0%V0 %1,%0\";
return \"#\";
}
diff --git a/gcc/testsuite/gcc.target/arc/add_n-combine.c
b/gcc/testsuite/gcc.target/arc/add_n-combine.c
index db6454f..cd32ed3 100644
--- a/gcc/testsuite/gcc.target/arc/add_n-combine.c
+++ b/gcc/testsuite/gcc.target/arc/add_n-combine.c
@@ -45,4 +45,4 @@ void f() {
a(at3.bn[bu]);
}
-/* { dg-final { scan-rtl-dump-times "\\*add_n" 3 "combine" } } */
+/* { dg-final { scan-rtl-dump-times "\\*add_n" 2 "combine" } } */
diff --git a/gcc/testsuite/gcc.target/arc/store-merge-1.c
b/gcc/testsuite/gcc.target/arc/store-merge-1.c
new file mode 100644
index 0000000..4bb8dcb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/store-merge-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+/* This tests checks if we use st w6,[reg] format. */
+
+typedef struct {
+ unsigned long __val[2];
+} sigset_t;
+
+int sigemptyset2 (sigset_t *set)
+{
+ set->__val[0] = 0;
+ set->__val[1] = 0;
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "st 0,\\\[r" 2 } } */
--
1.9.1
