Hi, On 29 May 2018 at 18:02, James Greenhalgh <james.greenha...@arm.com> wrote: > On Tue, May 29, 2018 at 10:28:27AM -0500, Kyrill Tkachov wrote: >> [sending on behalf of Jackson Woodruff] >> >> Hi all, >> >> This patch generalizes the formation of LDP/STP that require a base register. >> >> In AArch64, LDP/STP instructions have different sized immediate offsets than >> normal LDR/STR instructions. This part of the backend attempts to spot groups >> of four LDR/STR instructions that can be turned into LDP/STP instructions by >> using a base register. >> >> Previously, we would only accept address pairs that were ordered in ascending >> or descending order, and only strictly sequential loads/stores. In fact, the >> instructions that we generate from this should be able to consider any order >> of loads or stores (provided that they can be re-ordered). They should also >> be >> able to accept non-sequential loads and stores provided that the two pairs of >> addresses are amenable to pairing. The current code is also overly >> restrictive >> on the range of addresses that are accepted, as LDP/STP instructions may take >> negative offsets as well as positive ones. >> >> This patch improves that by allowing us to accept all orders of loads/stores >> that are valid, and extending the range that the LDP/STP addresses can reach. > > OK. >
The new test ldp_stp_10.c fails in ILP32 mode: FAIL: gcc.target/aarch64/ldp_stp_10.c scan-assembler-times ldp\tw[0-9]+, w[0-9]+, 2 FAIL: gcc.target/aarch64/ldp_stp_10.c scan-assembler-times ldp\tx[0-9]+, x[0-9]+, 2 Christophe > Thanks, > James > >