Robert Suchanek <robert.sucha...@mips.com> writes:
> As already discussed, the link to the P6600 doesn't
> appear to be referenced on mips.com but reachable
> when searching for 'p6600':
>
> https://www.mips.com/downloads/p6600-multiprocessing-programmers-guide/
Thanks, good spot.
> gcc/ChangeLog:
>
> 2018-06-12 Matthew Fortune <matthew.fort...@mips.com>
> Prachi Godbole <prachi.godb...@imgtec.com>
>
> * config/mips/mips-cpus.def: Define P6600.
> * config/mips/mips-tables.opt: Regenerate.
> * config/mips/mips.c (mips_ucbranch_type): New enum.
> (mips_rtx_cost_data): Add support for P6600.
> (mips_issue_rate): Likewise.
> (mips_multipass_dfa_lookahead): Likewise.
> (mips_avoid_hazard): Likewise.
> (mips_reorg_process_insns): Likewise.
> (mips_classify_branch_p6600): New function.
> * config/mips/mips.h (TUNE_P6600): New define.
> (MIPS_ISA_LEVEL_SPEC): Infer mips64r6 from p6600.
> (ENABLE_LD_ST_PAIRS): Enable load/store bonding for p6600.
> * config/mips/mips.md: Include p6600.md.
> (processor): Add p6600.
> * config/mips/p6600.md: New file.
> * doc/invoke.texi: Add p6600 to supported architectures.
With one more change to add another comment as below, this is OK to
commit.
> @@ -18957,7 +19039,10 @@ mips_reorg_process_insns (void)
> sequence and replace it with the delay slot instruction
> then the jump to clear the forbidden slot hazard. */
This bit does need the comment extending. Add this:
For the P6600, this optimisation solves the performance penalty
associated with BALC followed by a delay slot branch. We do not set
fs_delay as we do not want the full logic of a forbidden slot; the
penalty exists only against branches not the full class of forbidden
slot instructions.
>
> - if (fs_delay)
> + if (fs_delay || (TUNE_P6600
> + && TARGET_CB_MAYBE
> + && mips_classify_branch_p6600 (insn)
> + == UC_BALC))
> {
> /* Search onwards from the current position looking
> for
> a SEQUENCE. We are looking for pipeline hazards
here
Thanks,
Matthew
