On Fri, Jun 22, 2018 at 11:33:06AM -0600, Jeff Law wrote:
> On 06/13/2018 12:58 PM, Dimitar Dimitrov wrote:
> > The PRU load/store instructions can access memory with byte
> > granularity for all 30 of its 32-bit GP registers. Examples:
> >
> > # Load 17 bytes from address r0[0] into registers r10.b1-r14.b2
> > lbbo r10.b1, r0, 0, 17
> >
> > # Load 100 bytes from address r28[0] into registers r0-r25
> > lbbo r0.b0, r28, 0, 100
> >
> > The load/store multiple patterns declare all subsequent registers
> > as distinct operands. Hence the need to increase the limit.
Can't you have a look on how other targets, e.g. arm, aarch64, s390x
etc. handle load/store multiple patterns, e.g. with match_parallel or
match_par_dup?
The instructions then don't have dozens of operands, and the predicate
is just supposed to check everything is the way it should be.
Jakub
