Adds the ability to match movss and movsd as blend patterns,
implemented in a new method to be able to match these before shuffles,
while keeping other blends after.
2018-07-29 Allan Sandfeld Jensen <allan.jen...@qt.io>
gcc/config/i386
* i386.cc (expand_vec_perm_movs): New method matching movs
patterns.
* i386.cc (expand_vec_perm_1): Try the new method.
gcc/testsuite
* gcc.target/i386/sse2-movs.c: New test.
---
gcc/config/i386/emmintrin.h | 2 +-
gcc/config/i386/i386.c | 44 +++++++++++++++++++++++
gcc/config/i386/xmmintrin.h | 2 +-
gcc/testsuite/gcc.target/i386/sse2-movs.c | 21 +++++++++++
4 files changed, 67 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/sse2-movs.c
>From e96b3aa9017ad0d19238c923146196405cc4e5af Mon Sep 17 00:00:00 2001
From: Allan Sandfeld Jensen <allan.jen...@qt.io>
Date: Wed, 9 May 2018 12:35:14 +0200
Subject: [PATCH] Match movss and movsd blends
Adds the ability to match movss and movsd as blend patterns,
implemented in a new method to be able to match these before shuffles,
while keeping other blends after.
2018-07-29 Allan Sandfeld Jensen <allan.jen...@qt.io>
gcc/config/i386
* i386.cc (expand_vec_perm_movs): New method matching movs
patterns.
* i386.cc (expand_vec_perm_1): Try the new method.
gcc/testsuite
* gcc.target/i386/sse2-movs.c: New test.
---
gcc/config/i386/emmintrin.h | 2 +-
gcc/config/i386/i386.c | 44 +++++++++++++++++++++++
gcc/config/i386/xmmintrin.h | 2 +-
gcc/testsuite/gcc.target/i386/sse2-movs.c | 21 +++++++++++
4 files changed, 67 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/sse2-movs.c
diff --git a/gcc/config/i386/emmintrin.h b/gcc/config/i386/emmintrin.h
index b940a39d27b..1efd943bac4 100644
--- a/gcc/config/i386/emmintrin.h
+++ b/gcc/config/i386/emmintrin.h
@@ -113,7 +113,7 @@ _mm_setzero_pd (void)
extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_move_sd (__m128d __A, __m128d __B)
{
- return (__m128d) __builtin_ia32_movsd ((__v2df)__A, (__v2df)__B);
+ return __extension__ (__m128d)(__v2df){__B[0],__A[1]};
}
/* Load two DPFP values from P. The address must be 16-byte aligned. */
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index ee409cfe7e4..2337ef5ea08 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -46143,6 +46143,46 @@ expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
return ok;
}
+/* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
+ using movss or movsd. */
+static bool
+expand_vec_perm_movs (struct expand_vec_perm_d *d)
+{
+ machine_mode vmode = d->vmode;
+ unsigned i, nelt = d->nelt;
+ rtx x;
+
+ if (d->one_operand_p)
+ return false;
+
+ if (TARGET_SSE2 && (vmode == V2DFmode || vmode == V4SFmode))
+ ;
+ else
+ return false;
+
+ /* Only the first element is changed. */
+ if (d->perm[0] != nelt && d->perm[0] != 0)
+ return false;
+ for (i = 1; i < nelt; ++i) {
+ {
+ if (d->perm[i] != i + nelt - d->perm[0])
+ return false;
+ }
+ }
+
+ if (d->testing_p)
+ return true;
+
+ if (d->perm[0] == nelt)
+ x = gen_rtx_VEC_MERGE (vmode, d->op1, d->op0, GEN_INT (1));
+ else
+ x = gen_rtx_VEC_MERGE (vmode, d->op0, d->op1, GEN_INT (1));
+
+ emit_insn (gen_rtx_SET (d->target, x));
+
+ return true;
+}
+
/* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
@@ -46885,6 +46925,10 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d)
}
}
+ /* Try movss/movsd instructions. */
+ if (expand_vec_perm_movs (d))
+ return true;
+
/* Finally, try the fully general two operand permute. */
if (expand_vselect_vconcat (d->target, d->op0, d->op1, d->perm, nelt,
d->testing_p))
diff --git a/gcc/config/i386/xmmintrin.h b/gcc/config/i386/xmmintrin.h
index f64f3f74a0b..699f681e054 100644
--- a/gcc/config/i386/xmmintrin.h
+++ b/gcc/config/i386/xmmintrin.h
@@ -1011,7 +1011,7 @@ _mm_storer_ps (float *__P, __m128 __A)
extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_move_ss (__m128 __A, __m128 __B)
{
- return (__m128) __builtin_ia32_movss ((__v4sf)__A, (__v4sf)__B);
+ return __extension__ (__m128)(__v4sf){__B[0],__A[1],__A[2],__A[3]};
}
/* Extracts one of the four words of A. The selector N must be immediate. */
diff --git a/gcc/testsuite/gcc.target/i386/sse2-movs.c b/gcc/testsuite/gcc.target/i386/sse2-movs.c
new file mode 100644
index 00000000000..79f486cfa82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sse2-movs.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-final { scan-assembler "movss" } } */
+/* { dg-final { scan-assembler "movsd" } } */
+/* { dg-final { scan-assembler-not "unpcklps" } } */
+/* { dg-final { scan-assembler-not "shufps" } } */
+/* { dg-final { scan-assembler-not "shufpd" } } */
+
+typedef float v4sf __attribute__ ((vector_size (16)));
+typedef double v2df __attribute__ ((vector_size (16)));
+
+v4sf movss(v4sf a, v4sf b)
+{
+ return (v4sf){b[0],a[1],a[2],a[3]};
+}
+
+v2df movsd(v2df a, v2df b)
+{
+ return (v2df){b[0],a[1]};
+}
--
2.17.0
