On Tue, Jul 31, 2018 at 04:38:43AM -0500, Sam Tebbs wrote: > Hi all, > > This patch captures the case where an unnecessary uxtw instruction is > generated > after a bfxil instruction when in SI mode, and stops it from being > generated. > Note that this depends on my previous patch submission > (https://gcc.gnu.org/ml/gcc-patches/2018-07/msg01148.html). > > For example: > > unsigned long > combine_balanced_int (unsigned int a, unsigned int b) > { > return (a & 0xffff0000ll) | (b & 0x0000ffffll); > } > > Would generate: > > combine_balanced_int: > bfxil w0, w1, 0, 16 > uxtw x0, w0 > ret > > But with this patch generates: > > combine_balanced_int: > bfxil w0, w1, 0, 16 > ret > > Bootstrapped on aarch64-none-linux-gnu and regtested on aarch64-none-elf > with > no regressions.
OK once the other one is approved, with the obvious rebase over the renamed function. James > gcc/ > 2018-07-31 Sam Tebbs <sam.te...@arm.com> > > PR target/85628 > * config/aarch64/aarch64.md (*aarch64_bfxilsi_uxtw): Define. > > gcc/testsuite > 2018-07-31 Sam Tebbs <sam.te...@arm.com> > > PR target/85628 > * gcc.target/aarch64/combine_bfxil.c > (combine_zero_extended_int, foo6): > New functions.
