From 2871889515b9c7cc1af7bc93fe9e645b3adcd623 Mon Sep 17 00:00:00 2001
From: Chenghua Xu <[email protected]>
Date: Fri, 31 Aug 2018 11:55:48 +0800
Subject: [PATCH 3/6] [MIPS] Add support for Loongson EXT2 istructions.
gcc/
* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define
__mips_loongson_ext2, __mips_loongson_ext_rev=2.
(ISA_HAS_CTZ_CTO): New, ture if TARGET_LOONGSON_EXT2.
(ASM_SPEC): Add mloongson-ext2 and mno-loongson-ext2.
* config/mips/mips.md: Add ctz to "define_attr "type"".
(define_insn "ctz<mode>2"): New insn pattern.
(define_insn "prefetch"): Include TARGET_LOONGSON_EXT2.
* config/mips/mips.opt: Add -mloongson-ext2 option.
gcc/testsuite/
* gcc.target/mips/loongson-ctz.c: New test.
* gcc.target/mips/loongson-dctz.c: Likewise.
* gcc.target/mips/mips.exp (mips_option_groups): Add
-mloongson-ext2 option.
---
gcc/config/mips/mips.h | 12 +++++++++
gcc/config/mips/mips.md | 31 +++++++++++++++++++++----
gcc/config/mips/mips.opt | 4 +++
gcc/testsuite/gcc.target/mips/loongson-ctz.c | 11 +++++++++
gcc/testsuite/gcc.target/mips/loongson-dctz.c | 11 +++++++++
gcc/testsuite/gcc.target/mips/mips.exp | 1 +
6 files changed, 65 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/mips/loongson-ctz.c
create mode 100644 gcc/testsuite/gcc.target/mips/loongson-dctz.c
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index e0e78ba..b75646d 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -600,8 +600,16 @@ struct mips_cpu_info {
if (TARGET_LOONGSON_EXT) \
{ \
builtin_define ("__mips_loongson_ext"); \
+ if (TARGET_LOONGSON_EXT2) \
+ { \
+ builtin_define ("__mips_loongson_ext2"); \
+ builtin_define ("__mips_loongson_ext_rev=2"); \
+ } \
+ else \
+ builtin_define ("__mips_loongson_ext_rev=1"); \
} \
\
+ \
/* Historical Octeon macro. */ \
if (TARGET_OCTEON) \
builtin_define ("__OCTEON__"); \
@@ -1117,6 +1125,9 @@ struct mips_cpu_info {
/* ISA has count leading zeroes/ones instruction (not implemented). */
#define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
+/* ISA has count tailing zeroes/ones instruction (not implemented). */
+#define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2)
+
/* ISA has three operand multiply instructions that put
the high part in an accumulator: mulhi or mulhiu. */
#define ISA_HAS_MULHI ((TARGET_MIPS5400 \
@@ -1362,6 +1373,7 @@ struct mips_cpu_info {
%{mmsa} %{mno-msa} \
%{mloongson-mmi} %{mno-loongson-mmi} \
%{mloongson-ext} %{mno-loongson-ext} \
+%{mloongson-ext2} %{mno-loongson-ext2} \
%{msmartmips} %{mno-smartmips} \
%{mmt} %{mno-mt} \
%{mfix-rm7000} %{mno-fix-rm7000} \
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 4b7a627..c8128d4 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -335,6 +335,7 @@
;; slt set less than instructions
;; signext sign extend instructions
;; clz the clz and clo instructions
+;; ctz the ctz and cto instructions
;; pop the pop instruction
;; trap trap if instructions
;; imul integer multiply 2 operands
@@ -375,7 +376,7 @@
(define_attr "type"
"unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
- shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
+ shift,slt,signext,clz,ctz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
multi,atomic,syncloop,nop,ghost,multimem,
@@ -3149,6 +3150,23 @@
;;
;; ...................
;;
+;; Count tailing zeroes.
+;;
+;; ...................
+;;
+
+(define_insn "ctz<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (ctz:GPR (match_operand:GPR 1 "register_operand" "d")))]
+ "ISA_HAS_CTZ_CTO"
+ "<d>ctz\t%0,%1"
+ [(set_attr "type" "ctz")
+ (set_attr "mode" "<MODE>")])
+
+
+;;
+;; ...................
+;;
;; Count number of set bits.
;;
;; ...................
@@ -7136,13 +7154,16 @@
(match_operand 2 "const_int_operand" "n"))]
"ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
{
- if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT)
+ if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2)
{
- /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching. */
+ /* Loongson ext2 implementation pref insnstructions. */
+ if (TARGET_LOONGSON_EXT2)
+ return "pref\t%1, %a0";
+ /* Loongson 2[ef] and Loongson ext use load to $0 for prefetching. */
if (TARGET_64BIT)
- return "ld\t$0,%a0";
+ return "ld\t$0,%a0";
else
- return "lw\t$0,%a0";
+ return "lw\t$0,%a0";
}
operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
return "pref\t%1,%a0";
diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index a8fe8db..c0c8005 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -467,3 +467,7 @@ Use Loongson MultiMedia extensions Instructions (MMI) instructions.
mloongson-ext
Target Report Mask(LOONGSON_EXT)
Use Loongson EXTension (EXT) instructions.
+
+mloongson-ext2
+Target Report Mask(LOONGSON_EXT2)
+Use Loongson EXTension R2 (EXT2) instructions.
diff --git a/gcc/testsuite/gcc.target/mips/loongson-ctz.c b/gcc/testsuite/gcc.target/mips/loongson-ctz.c
new file mode 100644
index 0000000..8df66a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/loongson-ctz.c
@@ -0,0 +1,11 @@
+/* Test cases for Loongson EXT2 instrutions. */
+
+/* { dg-do compile } */
+/* { dg-options "-mloongson-ext2" } */
+
+unsigned int foo(unsigned int x)
+{
+ return __builtin_ctz (x);
+}
+
+/* { dg-final { scan-assembler "ctz\t" } } */
diff --git a/gcc/testsuite/gcc.target/mips/loongson-dctz.c b/gcc/testsuite/gcc.target/mips/loongson-dctz.c
new file mode 100644
index 0000000..8c47433
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/loongson-dctz.c
@@ -0,0 +1,11 @@
+/* Test cases for Loongson EXT2 instrutions. */
+
+/* { dg-do compile } */
+/* { dg-options "-mloongson-ext2" } */
+
+unsigned long long foo(unsigned long long x)
+{
+ return __builtin_ctzl (x);
+}
+
+/* { dg-final { scan-assembler "dctz\t" } } */
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp
index 70f7a99..5b2bf8b 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -298,6 +298,7 @@ foreach option {
msa
loongson-mmi
loongson-ext
+ loongson-ext2
} {
lappend mips_option_groups $option "-m(no-|)$option"
}
--
1.7.1
