Hi Kyrill, Thanks your reply.
On 2018/9/26 19:20, Kyrill Tkachov wrote: > Hi Shaokun, > > On 25/09/18 14:40, Zhangshaokun wrote: >> Hi ARM maintainers, >> >> Any plan to support CTR_EL0.DIC and CTR_EL0.IDC in GCC? >> I saw it has been supported in linux mainline(on Mar 7), >> Patch link: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2018-March/565090.html >> Kernel link: >> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/kernel/cpufeature.c?h=v4.19-rc5 >> +205 > > Do you mean implementing the data cache clearing elision in __clear_cache as > discussed in June [1]? Yes. > I am not aware of any plans to implement that support yet as we'd need > hardware to test this properly on. > Okay, got it. > If you can implement and test it and post it to the list I'm sure the > maintainers would be happy to review such patches though. > Sure, I will double check and test it again on certain HiSilicon platform. Thanks, Shaokun > Thanks, > Kyrill > > [1] https://gcc.gnu.org/ml/gcc-patches/2018-06/msg00307.html >> Thanks, >> Shaokun >> >> On 2018/9/20 22:22, James Greenhalgh wrote: >>> On Wed, Sep 19, 2018 at 04:53:52AM -0500, Shaokun Zhang wrote: >>>> This patch adds HiSilicon's an mcpu: tsv110, which supports v8_4A. >>>> It has been tested on aarch64 and no regressions from this patch. >>> This patch is OK for Trunk. >>> >>> Do you need someone to commit it on your behalf? >>> >>> Thanks, >>> James >>> >>>> --- >>>> gcc/ChangeLog | 9 +++ >>>> gcc/config/aarch64/aarch64-cores.def | 3 + >>>> gcc/config/aarch64/aarch64-cost-tables.h | 104 >>>> +++++++++++++++++++++++++++++++ >>>> gcc/config/aarch64/aarch64-tune.md | 2 +- >>>> gcc/config/aarch64/aarch64.c | 82 ++++++++++++++++++++++++ >>>> gcc/doc/invoke.texi | 2 +- >>>> 6 files changed, 200 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/gcc/ChangeLog b/gcc/ChangeLog >>>> index 69e2e14..a040daa 100644 >>>> --- a/gcc/ChangeLog >>>> +++ b/gcc/ChangeLog >>>> @@ -1,3 +1,12 @@ >>>> +2018-09-19 Shaokun Zhang <zhangshao...@hisilicon.com> >>>> + Bo Zhou <zbo.z...@hisilicon.com> >>>> + >>>> + * config/aarch64/aarch64-cores.def (tsv110): New CPU. >>>> + * config/aarch64/aarch64-tune.md: Regenerated. >>>> + * doc/invoke.texi (AArch64 Options/-mtune): Add "tsv110". >>>> + * config/aarch64/aarch64.c (tsv110_tunings): New tuning table. >>>> + * config/aarch64/aarch64-cost-tables.h: Add "tsv110" extra costs. >>>> + >>>> 2018-09-18 Marek Polacek <pola...@redhat.com> >>>> P1064R0 - Allowing Virtual Function Calls in Constant Expressions >>> >>> . >>> > > > . >
