Hi all, The mtune= documentation in doc/invoke.texi contains some obsolete CPU names that have been removed from the Arm and AArch64 backends. This patch removes them.
All removed CPU names: * arm2 * arm250 * arm3 * arm60 * arm600 * arm610 * arm620 * arm7 * arm7m * arm7d * arm7dm * arm7di * arm7dmi * arm70 * arm700 * arm700i * arm710 * arm710c * arm720 * arm7500 * arm7500fe This patch has no functional impact but has still been bootstrapped and regression tested on aarch64-none-elf. OK for trunk? gcc/ChangeLog: 2018-11-23 Sam Tebbs<sam.te...@arm.com> * doc/invoke.texi (-mtune=): Remove obsolete CPU names.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d46ebd02c4e0fee7b1c93a9e96d80113f6af93a7..0cda5421726f54f3ae7ccb9ab35b847e062ccb97 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -17157,21 +17157,13 @@ This option specifies the name of the target ARM processor for which GCC should tune the performance of the code. For some ARM implementations better performance can be obtained by using this option. -Permissible names are: @samp{arm2}, @samp{arm250}, -@samp{arm3}, @samp{arm6}, @samp{arm60}, @samp{arm600}, @samp{arm610}, -@samp{arm620}, @samp{arm7}, @samp{arm7m}, @samp{arm7d}, @samp{arm7dm}, -@samp{arm7di}, @samp{arm7dmi}, @samp{arm70}, @samp{arm700}, -@samp{arm700i}, @samp{arm710}, @samp{arm710c}, @samp{arm7100}, -@samp{arm720}, -@samp{arm7500}, @samp{arm7500fe}, @samp{arm7tdmi}, @samp{arm7tdmi-s}, -@samp{arm710t}, @samp{arm720t}, @samp{arm740t}, -@samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100}, -@samp{strongarm1110}, -@samp{arm8}, @samp{arm810}, @samp{arm9}, @samp{arm9e}, @samp{arm920}, -@samp{arm920t}, @samp{arm922t}, @samp{arm946e-s}, @samp{arm966e-s}, -@samp{arm968e-s}, @samp{arm926ej-s}, @samp{arm940t}, @samp{arm9tdmi}, -@samp{arm10tdmi}, @samp{arm1020t}, @samp{arm1026ej-s}, -@samp{arm10e}, @samp{arm1020e}, @samp{arm1022e}, +Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t}, +@samp{arm720t}, @samp{arm740t}, @samp{strongarm}, @samp{strongarm110}, +@samp{strongarm1100}, 0@samp{strongarm1110}, @samp{arm8}, @samp{arm810}, +@samp{arm9}, @samp{arm9e}, @samp{arm920}, @samp{arm920t}, @samp{arm922t}, +@samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm926ej-s}, +@samp{arm940t}, @samp{arm9tdmi}, @samp{arm10tdmi}, @samp{arm1020t}, +@samp{arm1026ej-s}, @samp{arm10e}, @samp{arm1020e}, @samp{arm1022e}, @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp}, @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s}, @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @@ -17180,22 +17172,12 @@ Permissible names are: @samp{arm2}, @samp{arm250}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, @samp{cortex-a76}, @samp{ares}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, -@samp{cortex-m33}, -@samp{cortex-m23}, -@samp{cortex-m7}, -@samp{cortex-m4}, -@samp{cortex-m3}, -@samp{cortex-m1}, -@samp{cortex-m0}, -@samp{cortex-m0plus}, -@samp{cortex-m1.small-multiply}, -@samp{cortex-m0.small-multiply}, -@samp{cortex-m0plus.small-multiply}, -@samp{exynos-m1}, -@samp{marvell-pj4}, -@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, -@samp{fa526}, @samp{fa626}, -@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, +@samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3}, +@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33}, +@samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply}, +@samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4}, +@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, +@samp{fa626}, @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{xgene1}. Additionally, this option can specify that GCC should tune the performance