On 19/12/2018 03:11, Shaokun Zhang wrote:
> For HiSilicon's tsv110 cpu core, it supports some v8_4A features, but
> some mandatory features are not implemented. Revert to ARMv8.2 that
> all mandatory features are supported.
>
Thanks, I've put this in.
I've modified the ChangeLog entry slightly - we normally use 'revert' in
the specific sense of completely removing an existing patch.
Also, when sending patches, please do not send ChangeLog entries as part
of the patch file. Because the file is always updated at the head, the
patch hunk is rarely going to apply cleanly. Instead, include the
ChangeLog text as part of your email description; that way we can then
paste it directly into the ChangeLog file itself and simply correct the
date.
R.
> ---
> gcc/ChangeLog | 5 +++++
> gcc/config/aarch64/aarch64-cores.def | 6 +++---
> 2 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> index e9f5baa6557c..842876b0ae90 100644
> --- a/gcc/ChangeLog
> +++ b/gcc/ChangeLog
> @@ -1,3 +1,8 @@
> +2018-12-19 Shaokun Zhang <zhangshao...@hisilicon.com>
> +
> + * config/aarch64/aarch64-cores.def (tsv110) : Revert support for ARMv8.2
> + in tsv110.
> +
> 2018-12-18 Vladimir Makarov <vmaka...@redhat.com>
>
> PR rtl-optimization/87759
> diff --git a/gcc/config/aarch64/aarch64-cores.def
> b/gcc/config/aarch64/aarch64-cores.def
> index 74be5dbf2595..20f4924e084d 100644
> --- a/gcc/config/aarch64/aarch64-cores.def
> +++ b/gcc/config/aarch64/aarch64-cores.def
> @@ -96,10 +96,10 @@ AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A,
> AARCH64_FL_FOR_ARCH8_2
> AARCH64_CORE("cortex-a76", cortexa76, cortexa57, 8_2A,
> AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC |
> AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1)
> AARCH64_CORE("ares", ares, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 |
> AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE,
> cortexa72, 0x41, 0xd0c, -1)
>
> -/* ARMv8.4-A Architecture Processors. */
> -
> /* HiSilicon ('H') cores. */
> -AARCH64_CORE("tsv110", tsv110, cortexa57, 8_4A,
> AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES
> | AARCH64_FL_SHA2, tsv110, 0x48, 0xd01, -1)
> +AARCH64_CORE("tsv110", tsv110, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 |
> AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2,
> tsv110, 0x48, 0xd01, -1)
> +
> +/* ARMv8.4-A Architecture Processors. */
>
> /* Qualcomm ('Q') cores. */
> AARCH64_CORE("saphira", saphira, saphira, 8_4A,
> AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira,
> 0x51, 0xC01, -1)
>
