On Mon, Feb 11, 2019 at 11:55 PM H.J. Lu <hjl.to...@gmail.com> wrote:
>
> Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
> by default with TARGET_MMX_WITH_SSE.
>
> For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
> mode since MMX intrinsics can be emulated wit SSE.
>
> gcc/
>
> PR target/89021
> * config/i386/i386-builtin.def: Enable MMX intrinsics with
> SSE/SSE2/SSSE3.
> * config/i386/i386.c (ix86_option_override_internal): Don't
> enable MMX ISA with TARGET_MMX_WITH_SSE by default.
> (bdesc_tm): Enable MMX intrinsics with SSE/SSE2/SSSE3.
> (ix86_init_mmx_sse_builtins): Likewise.
> (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX
> intrinsics with TARGET_MMX_WITH_SSE.
> * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.
>
> gcc/testsuite/
>
> PR target/89021
> * gcc.target/i386/pr82483-1.c: Error only on ia32.
> * gcc.target/i386/pr82483-2.c: Likewise.
> ---
> gcc/config/i386/i386-builtin.def | 126 +++++++++++-----------
> gcc/config/i386/i386.c | 62 +++++++----
> gcc/config/i386/mmintrin.h | 10 +-
> gcc/testsuite/gcc.target/i386/pr82483-1.c | 2 +-
> gcc/testsuite/gcc.target/i386/pr82483-2.c | 2 +-
> 5 files changed, 118 insertions(+), 84 deletions(-)
>
> diff --git a/gcc/config/i386/i386-builtin.def
> b/gcc/config/i386/i386-builtin.def
> index 88005f4687f..10a9d631f29 100644
> --- a/gcc/config/i386/i386-builtin.def
> +++ b/gcc/config/i386/i386-builtin.def
> @@ -100,7 +100,7 @@ BDESC (0, 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw",
> IX86_BUILTIN_FNSTSW, UNKN
> BDESC (0, 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX,
> UNKNOWN, (int) VOID_FTYPE_VOID)
>
> /* MMX */
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_emms, "__builtin_ia32_emms",
> IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_emms,
> "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID)
>
> /* 3DNow! */
> BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_femms, "__builtin_ia32_femms",
> IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID)
> @@ -442,68 +442,68 @@ BDESC (0, 0, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi",
> IX86_BUILTIN_RORQI, UNKNO
> BDESC (0, 0, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI,
> UNKNOWN, (int) UINT16_FTYPE_UINT16_INT)
>
> /* MMX */
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv8qi3,
> "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv4hi3,
> "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv2si3,
> "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv8qi3,
> "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv4hi3,
> "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv2si3,
> "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> -
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ssaddv8qi3,
> "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ssaddv4hi3,
> "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_sssubv8qi3,
> "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_sssubv4hi3,
> "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_usaddv8qi3,
> "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_usaddv4hi3,
> "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ussubv8qi3,
> "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ussubv4hi3,
> "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_mulv4hi3,
> "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_smulv4hi3_highpart,
> "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand",
> IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_andnotv2si3,
> "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por",
> IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor",
> IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> -
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv8qi3,
> "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv4hi3,
> "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv2si3,
> "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv8qi3,
> "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv4hi3,
> "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv2si3,
> "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> -
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhbw,
> "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhwd,
> "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhdq,
> "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpcklbw,
> "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpcklwd,
> "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckldq,
> "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> -
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packsswb,
> "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int)
> V8QI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packssdw,
> "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int)
> V4HI_FTYPE_V2SI_V2SI)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packuswb,
> "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int)
> V8QI_FTYPE_V4HI_V4HI)
> -
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_pmaddwd,
> "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int)
> V2SI_FTYPE_V4HI_V4HI)
> -
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv4hi3,
> "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv2si3,
> "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv1di3,
> "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int)
> V1DI_FTYPE_V1DI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv4hi3,
> "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv2si3,
> "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv1di3,
> "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int)
> V1DI_FTYPE_V1DI_V1DI_COUNT)
> -
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv4hi3,
> "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv2si3,
> "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv1di3,
> "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int)
> V1DI_FTYPE_V1DI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv4hi3,
> "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv2si3,
> "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv1di3,
> "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int)
> V1DI_FTYPE_V1DI_V1DI_COUNT)
> -
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv4hi3,
> "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv2si3,
> "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv4hi3,
> "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv2si3,
> "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv8qi3,
> "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv4hi3,
> "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv2si3,
> "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv8qi3,
> "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv4hi3,
> "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv2si3,
> "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> +
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB,
> UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB,
> UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB,
> UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB,
> UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_mulv4hi3,
> "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw",
> IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_andv2si3,
> "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN,
> UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_iorv2si3,
> "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_xorv2si3,
> "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> +
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv8qi3,
> "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv4hi3,
> "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv2si3,
> "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv8qi3,
> "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv4hi3,
> "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv2si3,
> "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> +
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW,
> UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ,
> UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW,
> UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ,
> UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> +
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packsswb,
> "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int)
> V8QI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packssdw,
> "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int)
> V4HI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packuswb,
> "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int)
> V8QI_FTYPE_V4HI_V4HI)
> +
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_pmaddwd,
> "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int)
> V2SI_FTYPE_V4HI_V4HI)
> +
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI,
> UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI,
> UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN,
> (int) V4HI_FTYPE_V4HI_V4HI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN,
> (int) V2SI_FTYPE_V2SI_V2SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN,
> (int) V1DI_FTYPE_V1DI_V1DI_COUNT)
> +
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI,
> UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI,
> UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN,
> (int) V4HI_FTYPE_V4HI_V4HI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN,
> (int) V2SI_FTYPE_V2SI_V2SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN,
> (int) V1DI_FTYPE_V1DI_V1DI_COUNT)
> +
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI,
> UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN,
> (int) V4HI_FTYPE_V4HI_V4HI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN,
> (int) V2SI_FTYPE_V2SI_V2SI_COUNT)
>
> /* 3DNow! */
> BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id",
> IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF)
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index 4e776b8c3ea..8b822b6d34f 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool main_args_p,
> opts->x_target_flags
> |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;
>
> - /* Enable by default the SSE and MMX builtins. Do allow the user to
> - explicitly disable any of these. In particular, disabling SSE and
> - MMX for kernel code is extremely useful. */
> + /* Enable the SSE and MMX builtins by default. Don't enable MMX
> + ISA with TARGET_MMX_WITH_SSE by default. Do allow the user to
> + explicitly disable any of these. In particular, disabling SSE
> + and MMX for kernel code is extremely useful. */
> if (!ix86_arch_specified)
> opts->x_ix86_isa_flags
> - |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
> + |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> + | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> + ? 0 : OPTION_MASK_ISA_MMX)
> | TARGET_SUBTARGET64_ISA_DEFAULT)
> & ~opts->x_ix86_isa_flags_explicit);
>
> @@ -4216,8 +4219,10 @@ ix86_option_override_internal (bool main_args_p,
> if (!TARGET_80387_P (opts->x_target_flags))
> opts->x_target_flags |= MASK_NO_FANCY_MATH_387;
>
> - /* Turn on MMX builtins for -msse. */
> - if (TARGET_SSE_P (opts->x_ix86_isa_flags))
> + /* Turn on MMX builtins for -msse. Don't enable MMX ISA with
> + TARGET_MMX_WITH_SSE. */
> + if (TARGET_SSE_P (opts->x_ix86_isa_flags)
> + && !TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))
> opts->x_ix86_isa_flags
> |= OPTION_MASK_ISA_MMX & ~opts->x_ix86_isa_flags_explicit;
>
> @@ -30810,13 +30815,13 @@ static const struct builtin_description
> bdesc_##kind[] = \
> we're lazy. Add casts to make them fit. */
> static const struct builtin_description bdesc_tm[] =
> {
> - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum
> ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum
> ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum
> ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum
> ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
> - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum
> ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
> - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum
> ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
> - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum
> ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
> + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN,
> VOID_FTYPE_PV2SI_V2SI },
> + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64,
> UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64,
> UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN,
> V2SI_FTYPE_PCV2SI },
> + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64,
> UNKNOWN, V2SI_FTYPE_PCV2SI },
> + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64,
> UNKNOWN, V2SI_FTYPE_PCV2SI },
> + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64,
> UNKNOWN, V2SI_FTYPE_PCV2SI },
Please explain why you need the above change.
> { OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum
> ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
> { OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM128",
> (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN,
> VOID_FTYPE_PV4SF_V4SF },
> @@ -30834,7 +30839,7 @@ static const struct builtin_description bdesc_tm[] =
> { OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM256",
> (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
> { OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM256",
> (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
>
> - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum
> ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
> + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN,
> VOID_FTYPE_PCVOID },
> { OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum
> ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
> { OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum
> ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
> };
> @@ -31509,14 +31514,17 @@ ix86_init_mmx_sse_builtins (void)
> VOID_FTYPE_UNSIGNED, IX86_BUILTIN_XABORT);
>
> /* MMX access to the vec_init patterns. */
> - def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v2si",
> + def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> + "__builtin_ia32_vec_init_v2si",
> V2SI_FTYPE_INT_INT, IX86_BUILTIN_VEC_INIT_V2SI);
>
> - def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v4hi",
> + def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> + "__builtin_ia32_vec_init_v4hi",
> V4HI_FTYPE_HI_HI_HI_HI,
> IX86_BUILTIN_VEC_INIT_V4HI);
>
> - def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v8qi",
> + def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> + "__builtin_ia32_vec_init_v8qi",
> V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
> IX86_BUILTIN_VEC_INIT_V8QI);
>
> @@ -31538,7 +31546,8 @@ ix86_init_mmx_sse_builtins (void)
> "__builtin_ia32_vec_ext_v4hi",
> HI_FTYPE_V4HI_INT, IX86_BUILTIN_VEC_EXT_V4HI);
>
> - def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_ext_v2si",
> + def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> + "__builtin_ia32_vec_ext_v2si",
> SI_FTYPE_V2SI_INT, IX86_BUILTIN_VEC_EXT_V2SI);
>
> def_builtin_const (OPTION_MASK_ISA_SSE2, 0, "__builtin_ia32_vec_ext_v16qi",
> @@ -36671,6 +36680,23 @@ ix86_expand_builtin (tree exp, rtx target, rtx
> subtarget,
> == (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))
> && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)
> isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);
> + /* Use SSE/SSE2/SSSE3 to emulate MMX intrinsics in 64-bit mode when
> + MMX is disabled. */
> + if (TARGET_MMX_WITH_SSE)
> + {
> + if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))
> + == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))
> + && (isa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) != 0)
> + isa |= (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX);
> + if (((bisa & (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX))
> + == (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX))
> + && (isa & (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX)) != 0)
> + isa |= (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX);
> + if (((bisa & (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX))
> + == (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX))
> + && (isa & (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX)) != 0)
> + isa |= (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX);
> + }
> if ((bisa & isa) != bisa || (bisa2 & isa2) != bisa2)
> {
> char *opts = ix86_target_string (bisa, bisa2, 0, 0, NULL, NULL,
> diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h
> index 238b3df3121..7b613658111 100644
> --- a/gcc/config/i386/mmintrin.h
> +++ b/gcc/config/i386/mmintrin.h
> @@ -30,7 +30,7 @@
> #if defined __x86_64__ && !defined __SSE__ || !defined __MMX__
> #pragma GCC push_options
> #ifdef __x86_64__
> -#pragma GCC target("sse,mmx")
> +#pragma GCC target("sse2")
> #else
> #pragma GCC target("mmx")
> #endif
> @@ -315,7 +315,11 @@ _m_paddd (__m64 __m1, __m64 __m2)
> /* Add the 64-bit values in M1 to the 64-bit values in M2. */
> #ifndef __SSE2__
> #pragma GCC push_options
> +#ifdef __x86_64__
> +#pragma GCC target("sse2")
> +#else
> #pragma GCC target("sse2,mmx")
> +#endif
> #define __DISABLE_SSE2__
> #endif /* __SSE2__ */
> @@ -427,7 +431,11 @@ _m_psubd (__m64 __m1, __m64 __m2)
> /* Add the 64-bit values in M1 to the 64-bit values in M2. */
> #ifndef __SSE2__
> #pragma GCC push_options
> +#ifdef __x86_64__
> +#pragma GCC target("sse2")
> +#else
> #pragma GCC target("sse2,mmx")
> +#endif
> #define __DISABLE_SSE2__
> #endif /* __SSE2__ */
Please also explain the need for the above changes.
Uros.
>
> diff --git a/gcc/testsuite/gcc.target/i386/pr82483-1.c
> b/gcc/testsuite/gcc.target/i386/pr82483-1.c
> index 59a59dc8dfe..b2028d8dc5e 100644
> --- a/gcc/testsuite/gcc.target/i386/pr82483-1.c
> +++ b/gcc/testsuite/gcc.target/i386/pr82483-1.c
> @@ -1,7 +1,7 @@
> /* PR target/82483 */
> /* { dg-do compile } */
> /* { dg-options "-mssse3 -mno-mmx -Wno-psabi" } */
> -/* { dg-error "needs isa option" "" { target *-*-* } 0 } */
> +/* { dg-error "needs isa option" "" { target ia32 } 0 } */
>
> #include <x86intrin.h>
>
> diff --git a/gcc/testsuite/gcc.target/i386/pr82483-2.c
> b/gcc/testsuite/gcc.target/i386/pr82483-2.c
> index 305ddbd6c64..c92de405cb3 100644
> --- a/gcc/testsuite/gcc.target/i386/pr82483-2.c
> +++ b/gcc/testsuite/gcc.target/i386/pr82483-2.c
> @@ -1,7 +1,7 @@
> /* PR target/82483 */
> /* { dg-do compile } */
> /* { dg-options "-mssse3 -mno-mmx -Wno-psabi" } */
> -/* { dg-error "needs isa option" "" { target *-*-* } 0 } */
> +/* { dg-error "needs isa option" "" { target ia32 } 0 } */
>
> #include <x86intrin.h>
>
> --
> 2.20.1
>
