On Tue, Feb 12, 2019 at 5:43 AM Uros Bizjak <ubiz...@gmail.com> wrote:
>
> On Mon, Feb 11, 2019 at 11:55 PM H.J. Lu <hjl.to...@gmail.com> wrote:
> >
> > PR target/89021
> > * config/i386/i386.c (ix86_expand_vector_init_duplicate): Set
> > mmx_ok to true if TARGET_MMX_WITH_SSE is true.
> > (ix86_expand_vector_init_one_nonzero): Likewise.
> > (ix86_expand_vector_init_one_var): Likewise.
> > (ix86_expand_vector_init_general): Likewise.
> > (ix86_expand_vector_init): Likewise.
> > (ix86_expand_vector_set): Likewise.
> > (ix86_expand_vector_extract): Likewise.
> > * config/i386/mmx.md (*vec_dupv2sf): Changed to
> > define_insn_and_split to support SSE emulation.
> > (vec_setv2sf): Also allow TARGET_MMX_WITH_SSE.
> > (vec_extractv2sf_1 splitter): Likewise.
> > (vec_extractv2sfsf): Likewise.
> > (vec_setv2si): Likewise.
> > (vec_extractv2si_1 splitter): Likewise.
> > (vec_extractv2sisi): Likewise.
> > (vec_setv4hi): Likewise.
> > (vec_extractv4hihi): Likewise.
> > (vec_setv8qi): Likewise.
> > (vec_extractv8qiqi): Likewise.
> > (*vec_extractv2sf_0): Don't allow TARGET_MMX_WITH_SSE.
> > (*vec_extractv2sf_1): Likewise.
> > (*vec_extractv2si_0): Likewise.
> > (*vec_extractv2si_1): Likewise.
> > (*vec_extractv2sf_0_sse): New.
> > (*vec_extractv2sf_1_sse): Likewise.
> > (*vec_extractv2si_0_sse): Likewise.
> > (*vec_extractv2si_1_sse): Likewise.
>
> Please do not introduce new *_sse patterns, use mmx_isa attribute to
> disable unwanted alternatives.
Will do.
> > (define_insn_and_split "*vec_extractv2si_zext_mem"
> > - [(set (match_operand:DI 0 "register_operand" "=y,x,r")
> > + [(set (match_operand:DI 0 "register_operand" "=x,r")
> > (zero_extend:DI
> > (vec_select:SI
> > - (match_operand:V2SI 1 "memory_operand" "o,o,o")
> > + (match_operand:V2SI 1 "memory_operand" "o,o")
> > (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))]
> > - "TARGET_64BIT && TARGET_MMX"
> > + "TARGET_64BIT"
>
> Here you need TARGET_64BIT && (TARGET_MMX || TARGET_MMX_WITH_SSE) and
> mmx_isa attribute.
>
Why is && (TARGET_MMX || TARGET_MMX_WITH_SSE) needed? The 3rd
alternative doesn't need MMX nor SSE2:
(define_insn_and_split "*vec_extractv2si_zext_mem"
[(set (match_operand:DI 0 "register_operand" "=y,x,r")
(zero_extend:DI
(vec_select:SI
(match_operand:V2SI 1 "memory_operand" "o,o,o")
(parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))]
"TARGET_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (zero_extend:DI (match_dup 1)))]
{
operands[1] = adjust_address (operands[1], SImode, INTVAL (operands[2]) * 4);
}
[(set_attr "mmx_isa" "native,sse2,base")])
--
H.J.
