On Tue, Apr 30, 2019 at 1:29 AM Jakub Jelinek <ja...@redhat.com> wrote: > From what I can see in riscv/sync.md, there is 32 bit and 64 bit compare and > swap, but not 16 bit (no idea why it doesn't emulate 8 bit and 16 bit > cas using 32 bit one).
This is a known problem on our to do list, and there is already a bugzilla or two about this. There are unfortunately a lot of items on our to do list as RISC-V is still a relatively new target. This is also complicated by the fact that we didn't have a formal memory model defined until last year, and now that we do have one, the gcc support needs to be updated to follow the formal memory model. There are a number of cleanup issues to fix here, such as the fact that we are emitting fences in places where the formal memory model says we don't need them. Anyways, we do want to fix this, but it is not clear when we will have time to do it. Jim
