This replaces the "wh" constraint by "d", with isa "p8v".
2019-05-21 Segher Boessenkool <seg...@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "wh"):
Delete.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_wh.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.md: Replace "wh" constraint by "wa" with "p8v".
* doc/md.texi (Machine Constraints): Adjust.
---
gcc/config/rs6000/constraints.md | 3 ---
gcc/config/rs6000/rs6000.c | 4 ----
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 20 ++++++++++++--------
gcc/doc/md.texi | 5 +----
5 files changed, 13 insertions(+), 20 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index dbcf08c..c9f168f 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -71,9 +71,6 @@ (define_register_constraint "wf"
"rs6000_constraints[RS6000_CONSTRAINT_wf]"
(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"
"If -mmfpgpr was used, a floating point register or NO_REGS.")
-(define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]"
- "Floating point register if direct moves are available, or NO_REGS.")
-
(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
"FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index b5dc5f3..a95848a 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2512,7 +2512,6 @@ rs6000_debug_reg_global (void)
"we reg_class = %s\n"
"wf reg_class = %s\n"
"wg reg_class = %s\n"
- "wh reg_class = %s\n"
"wi reg_class = %s\n"
"wj reg_class = %s\n"
"wk reg_class = %s\n"
@@ -2537,7 +2536,6 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
@@ -3163,7 +3161,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
wd - Preferred register class for V2DFmode.
wf - Preferred register class for V4SFmode.
wg - Float register for power6x move insns.
- wh - FP register for direct move instructions.
wi - FP or VSX register to hold 64-bit integers for VSX insns.
wj - FP or VSX register to hold 64-bit integers for direct moves.
wk - FP or VSX register to hold 64-bit doubles for direct moves.
@@ -3208,7 +3205,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_DIRECT_MOVE)
{
- rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */
= rs6000_constraints[RS6000_CONSTRAINT_wi];
rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index eaf309b..ca30639 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1253,7 +1253,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */
- RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */
RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */
RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct
moves. */
RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct
moves. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b2bba5d..398398c 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -471,7 +471,7 @@ (define_mode_attr zero_fp [(SF "j")
(define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
; Definitions for 64-bit direct move
-(define_mode_attr f64_dm [(DF "wk") (DD "wh")])
+(define_mode_attr f64_dm [(DF "wk") (DD "d")])
; Definitions for 64-bit use of altivec registers
(define_mode_attr f64_av [(DF "wv") (DD "wn")])
@@ -7349,10 +7349,10 @@ (define_insn "movsf_hardfloat"
;; FMR MR MT%0 MF%1 NOP
(define_insn "movsd_hardfloat"
[(set (match_operand:SD 0 "nonimmediate_operand"
- "=!r, wz, m, Z, ?wh, ?r,
+ "=!r, wz, m, Z, ?d, ?r,
f, !r, *c*l, !r, *h")
(match_operand:SD 1 "input_operand"
- "m, Z, r, wx, r, wh,
+ "m, Z, r, wx, r, d,
f, r, r, *h, 0"))]
"(register_operand (operands[0], SDmode)
|| register_operand (operands[1], SDmode))
@@ -7371,7 +7371,10 @@ (define_insn "movsd_hardfloat"
nop"
[(set_attr "type"
"load, fpload, store, fpstore, mffgpr, mftgpr,
- fpsimple, *, mtjmpr, mfjmpr, *")])
+ fpsimple, *, mtjmpr, mfjmpr, *")
+ (set_attr "isa"
+ "*, *, *, *, p8v, p8v,
+ *, *, *, *, *")])
;; MR MT%0 MF%0 LWZ STW LI
;; LIS G-const. F/n-const NOP
@@ -7684,7 +7687,7 @@ (define_insn "*mov<mode>_hardfloat64"
"*, *, *, p9v, p9v,
*, *, *, *, *,
*, *, *, *, *,
- *, *, *, *, *")])
+ *, *, *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -7737,8 +7740,8 @@ (define_expand "mov<mode>"
;; problematical. Don't allow direct move for this case.
(define_insn_and_split "*mov<mode>_64bit_dm"
- [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand"
"=m,d,d,d,Y,r,r,r,wh")
- (match_operand:FMOVE128_FPR 1 "input_operand"
"d,m,d,<zero_fp>,r,<zero_fp>Y,r,wh,r"))]
+ [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand"
"=m,d,d,d,Y,r,r,r,d")
+ (match_operand:FMOVE128_FPR 1 "input_operand"
"d,m,d,<zero_fp>,r,<zero_fp>Y,r,d,r"))]
"TARGET_HARD_FLOAT && TARGET_POWERPC64 && FLOAT128_2REG_P (<MODE>mode)
&& (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
&& (gpc_reg_operand (operands[0], <MODE>mode)
@@ -7747,7 +7750,8 @@ (define_insn_and_split "*mov<mode>_64bit_dm"
"&& reload_completed"
[(pc)]
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
- [(set_attr "length" "8,8,8,8,12,12,8,8,8")])
+ [(set_attr "length" "8,8,8,8,12,12,8,8,8")
+ (set_attr "isa" "*,*,*,*,*,*,*,p8v,p8v")])
(define_insn_and_split "*movtd_64bit_nodm"
[(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 6c7d121..daf0195 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3197,7 +3197,7 @@ Altivec vector register
Any VSX register if the @option{-mvsx} option was used or NO_REGS.
When using any of the register constraints (@code{wa}, @code{wd},
-@code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk},
+@code{wf}, @code{wg}, @code{wi}, @code{wj}, @code{wk},
@code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws},
@code{wt}, @code{wv}, or @code{ww})
that take VSX registers, you must use @code{%x<n>} in the template so
@@ -3259,9 +3259,6 @@ VSX vector register to hold vector float data or NO_REGS.
@item wg
If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
-@item wh
-Floating point register if direct moves are available, or NO_REGS.
-
@item wi
FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
--
1.8.3.1
