On 64-bit targets, 32-bit values are typically extended to 64-bits. So, the
32-bit
SImode operands in the xmpyu patterns end up being loaded as 64-bit values into
a
a floating-point register. The value is then implicitly narrowed to 32 bits by
pa_print_operand().
In the case the operand needs to be reloaded, we need to indicate to reload that
DI to SI mode class changes are okay. Otherwise, we end up with an invalid
SUBREG
insn. The attached change fixes this problem.
Tested on hppa64-hp-hpux11.11. Committed to active branches.
Dave
--
John David Anglin dave.ang...@bell.net
2019-05-24 John David Anglin <dang...@gcc.gnu.org>
PR target/90530
* config/pa/pa.c (pa_can_change_mode_class): Accept mode changes from
DImode to SImode in floating-point registers on 64-bit target.
* config/pa/pa.md (umulsidi3): Change nonimmediate_operand to
register_operand in xmpyu patterns.
Index: config/pa/pa.c
===================================================================
--- config/pa/pa.c (revision 271383)
+++ config/pa/pa.c (working copy)
@@ -10011,10 +10011,11 @@
/* There is no way to load QImode or HImode values directly from memory
to a FP register. SImode loads to the FP registers are not zero
extended. On the 64-bit target, this conflicts with the definition
- of LOAD_EXTEND_OP. Thus, we can't allow changing between modes with
- different sizes in the floating-point registers. */
+ of LOAD_EXTEND_OP. Thus, we reject all mode changes in the FP registers
+ except for DImode to SImode on the 64-bit target. It is handled by
+ register renaming in pa_print_operand. */
if (MAYBE_FP_REG_CLASS_P (rclass))
- return false;
+ return TARGET_64BIT && from == DImode && to == SImode;
/* TARGET_HARD_REGNO_MODE_OK places modes with sizes larger than a word
in specific sets of registers. Thus, we cannot allow changing
Index: config/pa/pa.md
===================================================================
--- config/pa/pa.md (revision 271383)
+++ config/pa/pa.md (working copy)
@@ -5319,8 +5319,8 @@
(define_insn "umulsidi3"
[(set (match_operand:DI 0 "register_operand" "=f")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"f"))
- (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand"
"f"))))]
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
+ (zero_extend:DI (match_operand:SI 2 "register_operand" "f"))))]
"TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
"xmpyu %1,%2,%0"
[(set_attr "type" "fpmuldbl")
@@ -5328,7 +5328,7 @@
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=f")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"f"))
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
(match_operand:DI 2 "uint32_operand" "f")))]
"TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT &&
!TARGET_64BIT"
"xmpyu %1,%R2,%0"
@@ -5337,7 +5337,7 @@
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=f")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"f"))
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
(match_operand:DI 2 "uint32_operand" "f")))]
"TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT &&
TARGET_64BIT"
"xmpyu %1,%2R,%0"
