<Fv2> always is "wa".
2019-06-04 Segher Boessenkool <seg...@kernel.crashing.org> * config/rs6000/rs6000.md (define_mode_attr Fv2): Delete. (rest of file): Adjust. --- gcc/config/rs6000/rs6000.md | 77 +++++++++++++++++++++------------------------ 1 file changed, 36 insertions(+), 41 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index a0628c1..8053d5a 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -528,11 +528,6 @@ (define_mode_attr Ff [(SF "f") (DF "d") (DI "d")]) ; format. (define_mode_attr Fv [(SF "ww") (DF "wa") (DI "wa")]) -; SF/DF constraint for arithmetic on VSX registers. This is intended to be -; used for DFmode instructions added in ISA 2.06 (power7) and SFmode -; instructions added in ISA 2.07 (power8) -(define_mode_attr Fv2 [(SF "wa") (DF "wa") (DI "wa")]) - ; Which isa is needed for those float instructions? (define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")]) @@ -4638,9 +4633,9 @@ (define_expand "add<mode>3" "") (define_insn "*add<mode>3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") - (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>") - (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa") + (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))] "TARGET_HARD_FLOAT" "@ fadd<Ftrad> %0,%1,%2 @@ -4656,9 +4651,9 @@ (define_expand "sub<mode>3" "") (define_insn "*sub<mode>3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") - (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>") - (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa") + (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))] "TARGET_HARD_FLOAT" "@ fsub<Ftrad> %0,%1,%2 @@ -4674,9 +4669,9 @@ (define_expand "mul<mode>3" "") (define_insn "*mul<mode>3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") - (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>") - (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa") + (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))] "TARGET_HARD_FLOAT" "@ fmul<Ftrad> %0,%1,%2 @@ -4700,9 +4695,9 @@ (define_expand "div<mode>3" }) (define_insn "*div<mode>3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") - (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>") - (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa") + (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))] "TARGET_HARD_FLOAT" "@ fdiv<Ftrad> %0,%1,%2 @@ -4711,8 +4706,8 @@ (define_insn "*div<mode>3_fpr" (set_attr "isa" "*,<Fisa>")]) (define_insn "*sqrt<mode>2_internal" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") - (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa") + (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")))] "TARGET_HARD_FLOAT && TARGET_PPC_GPOPT" "@ fsqrt<Ftrad> %0,%1 @@ -4739,8 +4734,8 @@ (define_expand "sqrt<mode>2" ;; Floating point reciprocal approximation (define_insn "fre<Fs>" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")] UNSPEC_FRES))] "TARGET_<FFRE>" "@ @@ -4750,8 +4745,8 @@ (define_insn "fre<Fs>" (set_attr "isa" "*,<Fisa>")]) (define_insn "*rsqrt<mode>2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")] UNSPEC_RSQRT))] "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)" "@ @@ -4763,8 +4758,8 @@ (define_insn "*rsqrt<mode>2" ;; Floating point comparisons (define_insn "*cmp<mode>_fpr" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y") - (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>") - (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))] + (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))] "TARGET_HARD_FLOAT" "@ fcmpu %0,%1,%2 @@ -13374,11 +13369,11 @@ (define_expand "fma<mode>4" "") (define_insn "*fma<mode>4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa") (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>,<Fv2>") - (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0") - (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>")))] + (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0") + (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa")))] "TARGET_HARD_FLOAT" "@ fmadd<Ftrad> %0,%1,%2,%3 @@ -13398,11 +13393,11 @@ (define_expand "fms<mode>4" "") (define_insn "*fms<mode>4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa") (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>") - (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0") - (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>"))))] + (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0") + (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa"))))] "TARGET_HARD_FLOAT" "@ fmsub<Ftrad> %0,%1,%2,%3 @@ -13445,12 +13440,12 @@ (define_expand "nfma<mode>4" "") (define_insn "*nfma<mode>4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa") (neg:SFDF (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>") - (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0") - (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>"))))] + (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0") + (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa"))))] "TARGET_HARD_FLOAT" "@ fnmadd<Ftrad> %0,%1,%2,%3 @@ -13471,13 +13466,13 @@ (define_expand "nfms<mode>4" "") (define_insn "*nfmssf4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa") (neg:SFDF (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>") - (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0") + (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0") (neg:SFDF - (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>")))))] + (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa")))))] "TARGET_HARD_FLOAT" "@ fnmsub<Ftrad> %0,%1,%2,%3 -- 1.8.3.1