As I detail in PR 91009, I had some testsuite failures with my patches for a
future machine. In the future patches, I added new RTL attributes to support
the new prefixed load/store instructions (which will include pc-relative
support). This new attribute needs to look at the 'type' RTL attribute, and
that in turn depends on doing a constrain operands to determine whether the
insn is a load, store, or add instruction.
This constrain operands call occurs before the first split pass. The insns
that convert SImode to SFmode or DFmode which are split in the first pass,
currently use the "wa" constraint for the floating point result. Unfortunately
if the user uses the -mno-vsx option, the "wa" constraint becomes NO_REGS.
This patch is a rather limited patch that just adds an alternative using the
"d" constraint, so there is a valid alternative before splitting.
This patch does not do the cleanup mentioned in PR 90822. That will still be
done, but I wanted to fix the actual problem before doing the next iteration of
the code cleanup.
I have done a bootstrap and make check, and there were no regressions. Can I
check this into the trunk?
2019-06-27 Michael Meissner <meiss...@linux.ibm.com>
PR target/91009
* config/rs6000/rs6000.md (floatsi<mode>2_lfiwax): Add non-VSX
alternative.
(floatsi<mode>2_lfiwax_mem): Add non-VSX alternative.
(floatunssi<mode>2_lfiwzx): Add non-VSX alternative.
(floatunssi<mode>2_lfiwzx_mem): Add non-VSX alternative.
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 272436)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -5227,9 +5227,9 @@ (define_insn "lfiwax"
; not be needed and also in case the insns are deleted as dead code.
(define_insn_and_split "floatsi<mode>2_lfiwax"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
- (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
- (clobber (match_scratch:DI 2 "=wa"))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+ (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r,r")))
+ (clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && TARGET_LFIWAX
&& <SI_CONVERT_FP> && can_create_pseudo_p ()"
"#"
@@ -5266,11 +5266,11 @@ (define_insn_and_split "floatsi<mode>2_l
(set_attr "type" "fpload")])
(define_insn_and_split "floatsi<mode>2_lfiwax_mem"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
(float:SFDF
(sign_extend:DI
- (match_operand:SI 1 "indexed_or_indirect_operand" "Z"))))
- (clobber (match_scratch:DI 2 "=wa"))]
+ (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
+ (clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && TARGET_LFIWAX && <SI_CONVERT_FP>"
"#"
""
@@ -5303,9 +5303,9 @@ (define_insn "lfiwzx"
(set_attr "isa" "*,p8v,p8v,p9v")])
(define_insn_and_split "floatunssi<mode>2_lfiwzx"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
- (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
- (clobber (match_scratch:DI 2 "=wa"))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+ (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r,r")))
+ (clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
"#"
""
@@ -5341,11 +5341,11 @@ (define_insn_and_split "floatunssi<mode>
(set_attr "type" "fpload")])
(define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
(unsigned_float:SFDF
(zero_extend:DI
- (match_operand:SI 1 "indexed_or_indirect_operand" "Z"))))
- (clobber (match_scratch:DI 2 "=wa"))]
+ (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
+ (clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
"#"
""
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
