On Mon, Jul 01, 2019 at 04:27:05PM -0500, Segher Boessenkool wrote: > Hi Mike, > > Sorry I missed this patch :-( > > On Thu, Jun 27, 2019 at 04:18:00PM -0400, Michael Meissner wrote: > > As we discussed off-line earlier, I changed all of the "4" lengths to be > > "*", > > even for instruction alternatives that would not be subject to being > > changed to > > be a prefixed instruction (i.e. the sign extend instruction "extsw"'s > > length is > > set to "*", even though it would not be a prefixed instruction). > > "*" means "use the default for this attribute", which often is nicer to > see than "4". For example, "8" stands out more in a sea of "*"s. > > Usually "*" is the insns defined as "normal" alternatives, and "8" or > "12" etc. are split. > > > @@ -7231,7 +7231,7 @@ (define_insn "*movcc_internal1" > > (const_string "mtjmpr") > > (const_string "load") > > (const_string "store")]) > > - (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")]) > > + (set_attr "length" "*,*,12,*,*,8,*,*,*,*,*,*")]) > > In this case, the "12" and "8" are actually defined as one insn in the > template, with some "\;". Luckily there aren't many of those. > > > @@ -7385,8 +7385,8 @@ (define_insn "*mov<mode>_softfloat" > > *, *, *, *") > > > > (set_attr "length" > > - "4, 4, 4, 4, 4, 4, > > - 4, 4, 8, 4")]) > > + "*, *, *, *, *, *, > > + *, *, 8, *")]) > > [ That last line should start with a tab as well. ]
Ok. > The entry before the 8 is split as well. Maybe that should be "4", to > stand out? I don't know what works better; your choice. Though the "G" constraint specifically says for SFmode it is a single instruction. > > @@ -7696,8 +7696,8 @@ (define_insn "*mov<mode>_softfloat64" > > *, *, *") > > > > (set_attr "length" > > - "4, 4, 4, 4, 4, 8, > > - 12, 16, 4")]) > > + "*, *, *, *, *, 8, > > + 12, 16, *")]) > > Same for the last entry here. Well technically that alternative will never fire (destination is "*h" and source is "0"), and a nop is emitted. I do wish we could never ever load floating point into SPR registers. I've tried in the reload days to eliminate it, but there was always some abort if it got eliminated. > > > @@ -8760,10 +8760,10 @@ (define_insn "*movdi_internal32" > > vecsimple") > > (set_attr "size" "64") > > (set_attr "length" > > - "8, 8, 8, 4, 4, 4, > > - 16, 4, 4, 4, 4, 4, > > - 4, 4, 4, 4, 4, 8, > > - 4") > > + "8, 8, 8, *, *, *, > > + 16, *, *, *, *, *, > > + *, *, *, *, *, 8, > > + *") > > And the last here. Well it will be split into a single VSPLTISW instruction. > > > @@ -8853,11 +8853,11 @@ (define_insn "*movdi_internal64" > > mftgpr, mffgpr") > > (set_attr "size" "64") > > (set_attr "length" > > - "4, 4, 4, 4, 4, 20, > > - 4, 4, 4, 4, 4, 4, > > - 4, 4, 4, 4, 4, 4, > > - 4, 8, 4, 4, 4, 4, > > - 4, 4") > > + "*, *, *, *, *, 20, > > + *, *, *, *, *, *, > > + *, *, *, *, *, *, > > + *, 8, *, *, *, *, > > + *, *") > > And two of the entries here. Though the second split becomes a single VSPLTISW instruction once again. > > @@ -1150,9 +1150,9 @@ (define_insn "vsx_mov<mode>_64bit" > > store, load, store, *, vecsimple, > > vecsimple, > > vecsimple, *, *, vecstore, vecload") > > (set_attr "length" > > - "4, 4, 4, 8, 4, 8, > > - 8, 8, 8, 8, 4, 4, > > - 4, 20, 8, 4, 4") > > + "*, *, *, 8, *, 8, > > + 8, 8, 8, 8, *, *, > > + *, 20, 8, *, *") > > No idea which ones are split here :-) None of the * and all other would > be nice, but who knows :-) Yeah, it gets complicated with LQ and STQ having such weird rules. > Okay for trunk, maybe with some "4" if you agree that has value. Thanks! > And again, sorry I missed this patch. NP. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797