On 11/24/2011 01:55 AM, Richard Earnshaw wrote: > That was deliberate. The ARM ARM says that it is unsafe to have any > other load or store instruction between an LDREX and its matching STREX. > If we split these instructions before the final scheduling operation > then there is a chance of that happening, which could lead to programs > failing to execute through such a block on some systems.
Except that the LDREX and STREX are both unspec_volatile, which will prevent anything from moving past them in the scheduler. The lack of other memory operations is ensured by waiting until after reload so that we don't wind up with register spills. Alpha can't have other memory operations between its LL/SC insns either, and we've successfully used post-reload splitting for years. r~
