The floating-point subtraction patterns don't need to handle
subtraction of constants, since those go through the addition
patterns instead. There was a missing MOVPRFX alternative for
FSUBR though.
Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf.
Applied as r274514.
Richard
2019-08-15 Richard Sandiford <richard.sandif...@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (*sub<SVE_F:mode>3): Remove immediate
FADD and FSUB alternatives. Add a MOVPRFX alternative for FSUBR.
Index: gcc/config/aarch64/aarch64-sve.md
===================================================================
--- gcc/config/aarch64/aarch64-sve.md 2019-08-15 09:32:03.211125428 +0100
+++ gcc/config/aarch64/aarch64-sve.md 2019-08-15 09:33:35.554443513 +0100
@@ -2878,34 +2878,31 @@ (define_insn_and_rewrite "*cond_add<mode
;; ---- [FP] Subtraction
;; -------------------------------------------------------------------------
;; Includes:
-;; - FADD
;; - FSUB
;; - FSUBR
;; -------------------------------------------------------------------------
;; Predicated floating-point subtraction.
(define_insn_and_split "*sub<mode>3"
- [(set (match_operand:SVE_F 0 "register_operand" "=w, w, w, w")
+ [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w")
(unspec:SVE_F
- [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl")
- (match_operand:SI 4 "aarch64_sve_gp_strictness" "i, i, i, Z")
- (match_operand:SVE_F 2 "aarch64_sve_float_arith_operand" "0, 0, vsA,
w")
- (match_operand:SVE_F 3 "aarch64_sve_float_arith_with_sub_operand"
"vsA, vsN, 0, w")]
+ [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
+ (match_operand:SI 4 "aarch64_sve_gp_strictness" "i, Z, i")
+ (match_operand:SVE_F 2 "aarch64_sve_float_arith_operand" "vsA, w,
vsA")
+ (match_operand:SVE_F 3 "register_operand" "0, w, 0")]
UNSPEC_COND_FSUB))]
- "TARGET_SVE
- && (register_operand (operands[2], <MODE>mode)
- || register_operand (operands[3], <MODE>mode))"
+ "TARGET_SVE"
"@
- fsub\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
- fadd\t%0.<Vetype>, %1/m, %0.<Vetype>, #%N3
fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2
- #"
+ #
+ movprfx\t%0, %3\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2"
; Split the unpredicated form after reload, so that we don't have
; the unnecessary PTRUE.
"&& reload_completed
- && register_operand (operands[2], <MODE>mode)
- && register_operand (operands[3], <MODE>mode)"
+ && register_operand (operands[2], <MODE>mode)"
[(set (match_dup 0) (minus:SVE_F (match_dup 2) (match_dup 3)))]
+ ""
+ [(set_attr "movprfx" "*,*,yes")]
)
;; Predicated floating-point subtraction from a constant, merging with the
