Hi Christophe, Thanks for pointing this out, uploaded a fix.
Regards, Yuliang From: Christophe Lyon <christophe.l...@linaro.org> Sent: 04 October 2019 09:25 To: Richard Sandiford <richard.sandif...@arm.com> Cc: Yuliang Wang <yuliang.w...@arm.com>; gcc-patches@gcc.gnu.org; nd <n...@arm.com> Subject: Re: [AArch64][SVE2] Shift-Right Accumulate combine patterns On Fri, 27 Sep 2019 at 10:12, Richard Sandiford <richard.sandif...@arm.com<mailto:richard.sandif...@arm.com>> wrote: Yuliang Wang <yuliang.w...@arm.com<mailto:yuliang.w...@arm.com>> writes: > Hi, > > This patch adds combining support for SVE2's shift-right accumulate > instructions. > > Example snippet: > > #define IMM ... > > void foo (TYPE a, TYPE b, int n) > { > for (int i = 0; i < n; i++) > a[i] += b[i] >> IMM; > } > > Signed: > > before asr z0.s, z0.s, #{IMM} > add z0.s, z0.s, z1.s > ... > after ssra z0.s, z1.s, #{IMM} > > Unsigned: > > before lsr z0.s, z0.s, #{IMM} > add z0.s, z0.s, z1.s > ... > after usra z0.s, z1.s, #{IMM} > > Built and regression tested on aarch64-none-elf. > > Best Regards, > Yuliang Wang > > > gcc/ChangeLog: > > 2019-09-26 Yuliang Wang <yuliang.w...@arm.com<mailto:yuliang.w...@arm.com>> > > * config/aarch64/aarch64-sve2.md (aarch64_sve2_sra<mode>): > New combine pattern. > > gcc/testsuite/ChangeLog: > > 2019-09-26 Yuliang Wang <yuliang.w...@arm.com<mailto:yuliang.w...@arm.com>> > > * gcc.target/aarch64/sve2/shracc_1.c: New test. Thanks, applied as r276174. Hi, I've noticed that the new test fails with -mabi=ilp32 Christophe Richard
