On Thu, Oct 17, 2019 at 01:46:41PM +1030, Alan Modra wrote: > On Sat, Oct 12, 2019 at 05:39:51PM -0500, Segher Boessenkool wrote: > > On Sat, Oct 12, 2019 at 10:13:16PM +0100, Iain Sandoe wrote: > > > For 32bit cases this isn't a problem since we can load/store to unaligned > > > addresses using D-mode insns. > > > > Can you? -m32 -mpowerpc64? We did have a bug with this before, maybe > > six years ago or so... Alan, do you remember? It required some assembler > > work IIRC. > > Yes, the ppc32 ABI doesn't have the relocs to support DS fields. > Rather than defining a whole series of _DS (and _DQ!) relocs, the > linker inspects the instruction being relocated and complains if the > relocation would modify opcode bits. See is_insn_ds_form in > bfd/elf32-ppc.c. We do the same on ppc64 for DQ field insns.
Ah right, that was it. So it uses the D reloc but with DS or DQ restrictions. Gotcha. For the compiler this is just as if those DS and DQ relocs *do* exist. > > I'll have another looke through this (esp. the generic part) when I'm fresh > > awake (but not before coffee!). Alan, can you have a look as well please? > > It looks reasonable to me. Thanks Alan! Segher
