PING
On Mon, Nov 11, 2019 at 4:42 PM Claudiu Zissulescu <claz...@gmail.com> wrote:
>
> Hi,
>
> Fix ARC specific tests by improving the matching pattern and adding
> the missing functionality in arc.exp
>
>
> OK to appy?
> Claudiu
>
>
> gcc/tests
> xxxx-xx-xx Claudiu Zissulescu <claz...@synopsys.com>
>
> * gcc.target/arc/add_n-combine.c: Match add1/2/3 instruction in
> output assembly.
> * gcc.target/arc/arc.exp (check_effective_target_codedensity):
> Add.
> * gcc.target/arc/cmem-7.c: Fix matching patterns.
> * gcc.target/arc/cmem-bit-1.c: Likewise.
> * gcc.target/arc/cmem-bit-2.c: Likewise.
> * gcc.target/arc/cmem-bit-3.c: Likewise.
> * gcc.target/arc/cmem-bit-4.c: Likewise.
> * gcc.target/arc/interrupt-2.c: Match rtie insn for A7.
> * gcc.target/arc/store-merge-1.c: This test is only meaningful for
> architectures with double load/store operations.
> ---
> gcc/testsuite/gcc.target/arc/add_n-combine.c | 6 ++++--
> gcc/testsuite/gcc.target/arc/arc.exp | 10 ++++++++++
> gcc/testsuite/gcc.target/arc/cmem-7.c | 8 ++++----
> gcc/testsuite/gcc.target/arc/cmem-bit-1.c | 4 ++--
> gcc/testsuite/gcc.target/arc/cmem-bit-2.c | 4 ++--
> gcc/testsuite/gcc.target/arc/cmem-bit-3.c | 4 ++--
> gcc/testsuite/gcc.target/arc/cmem-bit-4.c | 4 ++--
> gcc/testsuite/gcc.target/arc/interrupt-2.c | 3 ++-
> gcc/testsuite/gcc.target/arc/store-merge-1.c | 3 ++-
> 9 files changed, 30 insertions(+), 16 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/arc/add_n-combine.c
> b/gcc/testsuite/gcc.target/arc/add_n-combine.c
> index cd32ed386f5..bc400df669e 100644
> --- a/gcc/testsuite/gcc.target/arc/add_n-combine.c
> +++ b/gcc/testsuite/gcc.target/arc/add_n-combine.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -fdump-rtl-combine" } */
> +/* { dg-options "-O2" } */
>
> struct b1 {
> char c;
> @@ -45,4 +45,6 @@ void f() {
> a(at3.bn[bu]);
> }
>
> -/* { dg-final { scan-rtl-dump-times "\\*add_n" 2 "combine" } } */
> +/* { dg-final { scan-assembler "add1" } } */
> +/* { dg-final { scan-assembler "add2" } } */
> +/* { dg-final { scan-assembler "add3" } } */
> diff --git a/gcc/testsuite/gcc.target/arc/arc.exp
> b/gcc/testsuite/gcc.target/arc/arc.exp
> index 55e12137a2a..ac1d5b67048 100644
> --- a/gcc/testsuite/gcc.target/arc/arc.exp
> +++ b/gcc/testsuite/gcc.target/arc/arc.exp
> @@ -94,6 +94,16 @@ proc check_effective_target_barrelshifter { } {
> }]
> }
>
> +#return 1 if we have code density option on.
> +proc check_effective_target_codedensity { } {
> + return [check_no_compiler_messages codedensity assembly {
> + #if !defined(__ARC_CODE_DENSITY__)
> + #error No code density option for this config
> + #endif
> + }]
> +}
> +
> +
> #return 1 if we use ARCv2 Accumulator registers
> proc check_effective_target_accregs { } {
> return [check_no_compiler_messages accregs assembly {
> diff --git a/gcc/testsuite/gcc.target/arc/cmem-7.c
> b/gcc/testsuite/gcc.target/arc/cmem-7.c
> index 02673271172..ad7f25d9f8c 100644
> --- a/gcc/testsuite/gcc.target/arc/cmem-7.c
> +++ b/gcc/testsuite/gcc.target/arc/cmem-7.c
> @@ -21,7 +21,7 @@ some_function ()
> return 0;
> }
>
> -/* { dg-final { scan-assembler "xldb \[^\n\]*@ss" } } */
> -/* { dg-final { scan-assembler "xstb \[^\n\]*@ss" } } */
> -/* { dg-final { scan-assembler-not "xldb \[^\n\]*@tt" } } */
> -/* { dg-final { scan-assembler-not "xstb \[^\n\]*@tt" } } */
> +/* { dg-final { scan-assembler "xldb\\s+\[^\n\]*@ss" } } */
> +/* { dg-final { scan-assembler "xstb\\s+\[^\n\]*@ss" } } */
> +/* { dg-final { scan-assembler-not "xldb\\s+\[^\n\]*@tt" } } */
> +/* { dg-final { scan-assembler-not "xstb\\s+\[^\n\]*@tt" } } */
> diff --git a/gcc/testsuite/gcc.target/arc/cmem-bit-1.c
> b/gcc/testsuite/gcc.target/arc/cmem-bit-1.c
> index d49ab5cd44f..d3471a2e621 100644
> --- a/gcc/testsuite/gcc.target/arc/cmem-bit-1.c
> +++ b/gcc/testsuite/gcc.target/arc/cmem-bit-1.c
> @@ -16,5 +16,5 @@ void foo() {
> bar();
> }
>
> -/* { dg-final { scan-assembler "xldb r\[0-9\]+,\\\[@a_strange_bool\\\]" } }
> */
> -/* { dg-final { scan-assembler "btst_s r\[0-9\]+,7" { target arceb-*-* } } }
> */
> +/* { dg-final { scan-assembler "xldb\\s+r\[0-9\]+,\\\[@a_strange_bool\\\]" }
> } */
> +/* { dg-final { scan-assembler "btst_s\\s+r\[0-9\]+,7" { target arceb-*-* }
> } } */
> diff --git a/gcc/testsuite/gcc.target/arc/cmem-bit-2.c
> b/gcc/testsuite/gcc.target/arc/cmem-bit-2.c
> index 45b49c6dfc3..4b022944f60 100644
> --- a/gcc/testsuite/gcc.target/arc/cmem-bit-2.c
> +++ b/gcc/testsuite/gcc.target/arc/cmem-bit-2.c
> @@ -16,5 +16,5 @@ void foo() {
> bar();
> }
>
> -/* { dg-final { scan-assembler "xldb r\[0-9\]+,\\\[@a_strange_bool\\\]" } }
> */
> -/* { dg-final { scan-assembler "btst_s r\[0-9\]+,7" { target arceb-*-* } } }
> */
> +/* { dg-final { scan-assembler "xldb\\s+r\[0-9\]+,\\\[@a_strange_bool\\\]" }
> } */
> +/* { dg-final { scan-assembler "btst_s\\s+r\[0-9\]+,7" { target arceb-*-* }
> } } */
> diff --git a/gcc/testsuite/gcc.target/arc/cmem-bit-3.c
> b/gcc/testsuite/gcc.target/arc/cmem-bit-3.c
> index 371ff2bca8b..40fbb934bf9 100644
> --- a/gcc/testsuite/gcc.target/arc/cmem-bit-3.c
> +++ b/gcc/testsuite/gcc.target/arc/cmem-bit-3.c
> @@ -16,5 +16,5 @@ void foo() {
> bar();
> }
>
> -/* { dg-final { scan-assembler "xldb r\[0-9\]+,\\\[@a_strange_bool\\\]" } }
> */
> -/* { dg-final { scan-assembler "btst_s r\[0-9\]+,7" { target arceb-*-* } } }
> */
> +/* { dg-final { scan-assembler "xldb\\s+r\[0-9\]+,\\\[@a_strange_bool\\\]" }
> } */
> +/* { dg-final { scan-assembler "btst_s\\s+r\[0-9\]+,7" { target arceb-*-* }
> } } */
> diff --git a/gcc/testsuite/gcc.target/arc/cmem-bit-4.c
> b/gcc/testsuite/gcc.target/arc/cmem-bit-4.c
> index a95c6ae14d3..288a6a03583 100644
> --- a/gcc/testsuite/gcc.target/arc/cmem-bit-4.c
> +++ b/gcc/testsuite/gcc.target/arc/cmem-bit-4.c
> @@ -16,5 +16,5 @@ void foo() {
> bar();
> }
>
> -/* { dg-final { scan-assembler "xldb r\[0-9\]+,\\\[@a_strange_bool\\\]" } }
> */
> -/* { dg-final { scan-assembler "btst_s r\[0-9\]+,7" { target arceb-*-* } } }
> */
> +/* { dg-final { scan-assembler "xldb\\s+r\[0-9\]+,\\\[@a_strange_bool\\\]" }
> } */
> +/* { dg-final { scan-assembler "btst_s\\s+r\[0-9\]+,7" { target arceb-*-* }
> } } */
> diff --git a/gcc/testsuite/gcc.target/arc/interrupt-2.c
> b/gcc/testsuite/gcc.target/arc/interrupt-2.c
> index 285ebd57a22..09c6f4d216e 100644
> --- a/gcc/testsuite/gcc.target/arc/interrupt-2.c
> +++ b/gcc/testsuite/gcc.target/arc/interrupt-2.c
> @@ -3,4 +3,5 @@ void __attribute__ ((interrupt("ilink2")))
> handler1 (void)
> {
> }
> -/* { dg-final { scan-assembler-times "j.*\[ilink2\]" 1 } } */
> +/* { dg-final { scan-assembler-times "j.*\[ilink2\]" 1 { target { arc6xx } }
> } } */
> +/* { dg-final { scan-assembler-times "rtie" 1 { target { arc700 } } } } */
> diff --git a/gcc/testsuite/gcc.target/arc/store-merge-1.c
> b/gcc/testsuite/gcc.target/arc/store-merge-1.c
> index e9d4e57c27d..a133e8719b4 100644
> --- a/gcc/testsuite/gcc.target/arc/store-merge-1.c
> +++ b/gcc/testsuite/gcc.target/arc/store-merge-1.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-O3" } */
> +/* { dg-require-effective-target archs }*/
> +/* { dg-options "-O3 -mll64" } */
>
> /* This tests checks if we use st w6,[reg] format. */
>
> --
> 2.23.0
>
