On Sun, Dec 15, 2019 at 03:45:34PM -0700, Jeff Law wrote: > For x86, patterns which set/clobber the condition codes have explicit > sets/clobbers of the flags register. As a result the dataflow is > accurately represented and the optimizers don't really have to do > anything special. It's no different than cases there other hard > registers hold live data.
Yup. And since x86 uses a fixed register as CC, already the earliest passes cannot just create one anywhere. Compare to if it used pseudos: you can just create a fresh pseudo wherever you want, it is a new one, nothing refers to it yet, nothing can conflict with it. If you used pseudos although there is only one hard register that can be used, you end up with quite a lot of save/restore code, and those are typically expensive insns as well. Quite a bit worse than the lost optimisations you get from using a fixed register (insns cannot move as much, lifetimes have to stay short, but that's about it). > Contrast to a cc0 target (such as the H8 still in the tree). On a cc0 > target patterns which modify the condition codes do not describe them > at the RTL level (with the exception of cmp/tst insns). Dataflow is > incomplete and as a result, most RTL passes have to handle things > specially to avoid the situation you're worried about. Search for > HAVE_cc0. Only the insn immediately after a cc0 setter can use the value set (well, ignoring branch delay slots. Ignoring those is a great idea, unless you are unlucky enough to have to use them ;-) ). So it isn't hard to handle the "dataflow" for them, in principle, but it is special cases *everywhere*. Segher
