On Wed, Feb 05, 2020 at 11:48:23AM -0700, Jeff Law wrote: > Yea, it's closely related. In your case you need to effectively ignore > the nop insn to get the optimization you want. In mine that nop insn > causes an ICE. > > I think we could take your cse bits + adding a !CALL_P separately from > the simplify-rtx stuff which Segher objected to. THat'd likely solve > the ARM ICEs and take you a tiny step forward on optimizing that SVE > case. Thoughts?
CSE should consistently keep track of what insns are no-op moves (in its definition, all passes have a slightly different definition of this), and use that everywhere consistently. (Or we should rewrite CSE). Segher
