There is no need to set mode attribute to XImode nor V8DFmode since
ix86_output_ssemov can properly encode xmm16-xmm31 registers with and
without AVX512VL.

gcc/

        PR target/89229
        * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov
        for TYPE_SSEMOV.  Remove TARGET_AVX512F, TARGET_PREFER_AVX256,
        TARGET_AVX512VL and ext_sse_reg_operand check.

gcc/testsuite/

        PR target/89229
        * gcc.target/i386/pr89229-6a.c: New test.
        * gcc.target/i386/pr89229-6b.c: Likewise.
        * gcc.target/i386/pr89229-6c.c: Likewise.
---
 gcc/config/i386/i386.md                    | 44 ++--------------------
 gcc/testsuite/gcc.target/i386/pr89229-6a.c | 16 ++++++++
 gcc/testsuite/gcc.target/i386/pr89229-6b.c |  7 ++++
 gcc/testsuite/gcc.target/i386/pr89229-6c.c |  6 +++
 4 files changed, 32 insertions(+), 41 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-6a.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-6b.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-6c.c

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index fdf0e5a8802..01892992adb 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -3307,37 +3307,7 @@ (define_insn "*movdf_internal"
       return standard_sse_constant_opcode (insn, operands);
 
     case TYPE_SSEMOV:
-      switch (get_attr_mode (insn))
-       {
-       case MODE_DF:
-         if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
-           return "vmovsd\t{%d1, %0|%0, %d1}";
-         return "%vmovsd\t{%1, %0|%0, %1}";
-
-       case MODE_V4SF:
-         return "%vmovaps\t{%1, %0|%0, %1}";
-       case MODE_V8DF:
-         return "vmovapd\t{%g1, %g0|%g0, %g1}";
-       case MODE_V2DF:
-         return "%vmovapd\t{%1, %0|%0, %1}";
-
-       case MODE_V2SF:
-         gcc_assert (!TARGET_AVX);
-         return "movlps\t{%1, %0|%0, %1}";
-       case MODE_V1DF:
-         gcc_assert (!TARGET_AVX);
-         return "movlpd\t{%1, %0|%0, %1}";
-
-       case MODE_DI:
-         /* Handle broken assemblers that require movd instead of movq.  */
-         if (!HAVE_AS_IX86_INTERUNIT_MOVQ
-             && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
-           return "%vmovd\t{%1, %0|%0, %1}";
-         return "%vmovq\t{%1, %0|%0, %1}";
-
-       default:
-         gcc_unreachable ();
-       }
+      return ix86_output_ssemov (insn, operands);
 
     default:
       gcc_unreachable ();
@@ -3391,10 +3361,7 @@ (define_insn "*movdf_internal"
 
               /* xorps is one byte shorter for non-AVX targets.  */
               (eq_attr "alternative" "12,16")
-                (cond [(and (match_test "TARGET_AVX512F")
-                            (not (match_test "TARGET_PREFER_AVX256")))
-                         (const_string "XI")
-                       (match_test "TARGET_AVX")
+                (cond [(match_test "TARGET_AVX")
                          (const_string "V2DF")
                        (ior (not (match_test "TARGET_SSE2"))
                             (match_test "optimize_function_for_size_p (cfun)"))
@@ -3410,12 +3377,7 @@ (define_insn "*movdf_internal"
 
               /* movaps is one byte shorter for non-AVX targets.  */
               (eq_attr "alternative" "13,17")
-                (cond [(and (ior (not (match_test "TARGET_PREFER_AVX256"))
-                                 (not (match_test "TARGET_AVX512VL")))
-                            (ior (match_operand 0 "ext_sse_reg_operand")
-                                 (match_operand 1 "ext_sse_reg_operand")))
-                         (const_string "V8DF")
-                       (match_test "TARGET_AVX")
+                (cond [(match_test "TARGET_AVX")
                          (const_string "DF")
                        (ior (not (match_test "TARGET_SSE2"))
                             (match_test "optimize_function_for_size_p (cfun)"))
diff --git a/gcc/testsuite/gcc.target/i386/pr89229-6a.c 
b/gcc/testsuite/gcc.target/i386/pr89229-6a.c
new file mode 100644
index 00000000000..5bc10d25619
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-6a.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512" } */
+
+extern double d;
+
+void
+foo1 (double x)
+{
+  register double xmm16 __asm ("xmm16") = x;
+  asm volatile ("" : "+v" (xmm16));
+  register double xmm17 __asm ("xmm17") = xmm16;
+  asm volatile ("" : "+v" (xmm17));
+  d = xmm17;
+}
+
+/* { dg-final { scan-assembler-not "vmovapd" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr89229-6b.c 
b/gcc/testsuite/gcc.target/i386/pr89229-6b.c
new file mode 100644
index 00000000000..b248a3726f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-6b.c
@@ -0,0 +1,7 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512 -mno-avx512vl" } */
+
+#include "pr89229-6a.c"
+
+/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "vmovapd" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr89229-6c.c 
b/gcc/testsuite/gcc.target/i386/pr89229-6c.c
new file mode 100644
index 00000000000..7a4d254670c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-6c.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512 -mprefer-vector-width=512" } */
+
+#include "pr89229-6a.c"
+
+/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
-- 
2.24.1

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