There is no need to set mode attribute to XImode since ix86_output_ssemov can properly encode xmm16-xmm31 registers with and without AVX512VL.
Remove ext_sse_reg_operand since it is no longer needed. PR target/89229 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_V1DF and MODE_V2SF. * config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand check. * config/i386/predicates.md (ext_sse_reg_operand): Removed. --- gcc/config/i386/i386.c | 10 ++++++++++ gcc/config/i386/mmx.md | 29 ++--------------------------- gcc/config/i386/predicates.md | 5 ----- 3 files changed, 12 insertions(+), 32 deletions(-) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 1d3b784532b..f34a708cdc3 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -5142,6 +5142,16 @@ ix86_output_ssemov (rtx_insn *insn, rtx *operands) else return "%vmovss\t{%1, %0|%0, %1}"; + case MODE_V1DF: + gcc_assert (!TARGET_AVX); + return "movlpd\t{%1, %0|%0, %1}"; + + case MODE_V2SF: + if (TARGET_AVX && REG_P (operands[0])) + return "vmovlps\t{%1, %d0|%d0, %1}"; + else + return "%vmovlps\t{%1, %0|%0, %1}"; + default: gcc_unreachable (); } diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index e1c8b0af4c7..c3f195bb34a 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -118,29 +118,7 @@ (define_insn "*mov<mode>_internal" return standard_sse_constant_opcode (insn, operands); case TYPE_SSEMOV: - switch (get_attr_mode (insn)) - { - case MODE_DI: - /* Handle broken assemblers that require movd instead of movq. */ - if (!HAVE_AS_IX86_INTERUNIT_MOVQ - && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) - return "%vmovd\t{%1, %0|%0, %1}"; - return "%vmovq\t{%1, %0|%0, %1}"; - case MODE_TI: - return "%vmovdqa\t{%1, %0|%0, %1}"; - case MODE_XI: - return "vmovdqa64\t{%g1, %g0|%g0, %g1}"; - - case MODE_V2SF: - if (TARGET_AVX && REG_P (operands[0])) - return "vmovlps\t{%1, %0, %0|%0, %0, %1}"; - return "%vmovlps\t{%1, %0|%0, %1}"; - case MODE_V4SF: - return "%vmovaps\t{%1, %0|%0, %1}"; - - default: - gcc_unreachable (); - } + return ix86_output_ssemov (insn, operands); default: gcc_unreachable (); @@ -189,10 +167,7 @@ (define_insn "*mov<mode>_internal" (cond [(eq_attr "alternative" "2") (const_string "SI") (eq_attr "alternative" "11,12") - (cond [(ior (match_operand 0 "ext_sse_reg_operand") - (match_operand 1 "ext_sse_reg_operand")) - (const_string "XI") - (match_test "<MODE>mode == V2SFmode") + (cond [(match_test "<MODE>mode == V2SFmode") (const_string "V4SF") (ior (not (match_test "TARGET_SSE2")) (match_test "optimize_function_for_size_p (cfun)")) diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 1119366d54e..71f4cb1193c 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -61,11 +61,6 @@ (define_predicate "sse_reg_operand" (and (match_code "reg") (match_test "SSE_REGNO_P (REGNO (op))"))) -;; True if the operand is an AVX-512 new register. -(define_predicate "ext_sse_reg_operand" - (and (match_code "reg") - (match_test "EXT_REX_SSE_REGNO_P (REGNO (op))"))) - ;; Return true if op is a QImode register. (define_predicate "any_QIreg_operand" (and (match_code "reg") -- 2.24.1