On Tue, Mar 3, 2020 at 10:41 AM Claudiu Zissulescu <claz...@gmail.com> wrote:
>
> The mmixed-code option is obsolete, remove it.
You might want to preserve the option and ignore it like we do
for some in common.opt:
fargument-alias
Common Ignore
Does nothing. Preserved for backward compatibility.
this avoids compiler errors when updating the compiler but not
adjusting flags.
Richard.
> gcc/
> xxxx-xx-xx Claudiu Zissulescu <claz...@synopsys.com>
>
> * config/arc/arc.c (arc_override_options): Remove
> TARGET_MIXED_CODE reference.
> * config/arc/arc.md (abssi2_mixed): Remove pattern.
> * config/arc/arc.h (TARGET_MIXED_CODE): Remove macro.
> (INDEX_REG_CLASS): Only refer to GENERAL_REGS.
> * config/arc/arc.opt (mmixed-code): Remove option.
> * doc/invoke.texi (ARC): Remove mmixed-code doc.
> ---
> gcc/config/arc/arc.h | 4 +---
> gcc/config/arc/arc.md | 8 --------
> gcc/config/arc/arc.opt | 8 --------
> gcc/doc/invoke.texi | 8 +-------
> 4 files changed, 2 insertions(+), 26 deletions(-)
>
> diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
> index b7fa7ba8fa3..21ffeee9ad2 100644
> --- a/gcc/config/arc/arc.h
> +++ b/gcc/config/arc/arc.h
> @@ -115,8 +115,6 @@ extern const char *arc_cpu_to_as (int argc, const char
> **argv);
>
> /* Run-time compilation parameters selecting different hardware subsets. */
>
> -#define TARGET_MIXED_CODE (TARGET_MIXED_CODE_SET)
> -
> #define TARGET_SPFP (TARGET_SPFP_FAST_SET || TARGET_SPFP_COMPACT_SET)
> #define TARGET_DPFP (TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET \
> || TARGET_FP_DP_AX)
> @@ -571,7 +569,7 @@ extern enum reg_class arc_regno_reg_class[];
> a scale factor or added to another register (as well as added to a
> displacement). */
>
> -#define INDEX_REG_CLASS (TARGET_MIXED_CODE ? ARCOMPACT16_REGS : GENERAL_REGS)
> +#define INDEX_REG_CLASS GENERAL_REGS
>
> /* The class value for valid base registers. A base register is one used in
> an address which is the register value plus a displacement. */
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index a26a7a4dd5f..e1958fda2e6 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -2001,14 +2001,6 @@ archs4x, archs4xd"
>
> ;; Absolute instructions
>
> -(define_insn "*abssi2_mixed"
> - [(set (match_operand:SI 0 "compact_register_operand" "=q")
> - (abs:SI (match_operand:SI 1 "compact_register_operand" "q")))]
> - "TARGET_MIXED_CODE"
> - "abs%? %0,%1%&"
> - [(set_attr "type" "two_cycle_core")
> - (set_attr "iscompact" "true")])
> -
> (define_insn "abssi2"
> [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,w,w")
> (abs:SI (match_operand:SI 1 "nonmemory_operand" "Rcq#q,cL,Cal")))]
> diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt
> index deaf306739e..2b2b947ca08 100644
> --- a/gcc/config/arc/arc.opt
> +++ b/gcc/config/arc/arc.opt
> @@ -135,14 +135,6 @@ mcode-density
> Target Report Mask(CODE_DENSITY)
> Enable code density instructions for ARCv2.
>
> -mmixed-code
> -Target Report Mask(MIXED_CODE_SET)
> -Tweak register allocation to help 16-bit instruction generation.
> -; originally this was:
> -;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
> -; but we do that without -mmixed-code, too, it's just a different instruction
> -; count / size tradeoff.
> -
> ; We use an explict definition for the negative form because that is the
> ; actually interesting option, and we want that to have its own comment.
> mvolatile-cache
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 8c6c90217f4..7627e889b5d 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -727,7 +727,7 @@ Objective-C and Objective-C++ Dialects}.
> -mcase-vector-pcrel -mcompact-casesi -mno-cond-exec -mearly-cbranchsi @gol
> -mexpand-adddi -mindexed-loads -mlra -mlra-priority-none @gol
> -mlra-priority-compact mlra-priority-noncompact -mmillicode @gol
> --mmixed-code -mq-class -mRcq -mRcw -msize-level=@var{level} @gol
> +-mq-class -mRcq -mRcw -msize-level=@var{level} @gol
> -mtune=@var{cpu} -mmultcost=@var{num} -mcode-density-frame @gol
> -munalign-prob-threshold=@var{probability} -mmpy-option=@var{multo} @gol
> -mdiv-rem -mcode-density -mll64 -mfpu=@var{fpu} -mrf16 -mbranch-index}
> @@ -17956,12 +17956,6 @@ This option enable the compiler to emit @code{enter}
> and @code{leave}
> instructions. These instructions are only valid for CPUs with
> code-density feature.
>
> -@item -mmixed-code
> -@opindex mmixed-code
> -Tweak register allocation to help 16-bit instruction generation.
> -This generally has the effect of decreasing the average instruction size
> -while increasing the instruction count.
> -
> @item -mq-class
> @opindex mq-class
> Ths option is deprecated. Enable @samp{q} instruction alternatives.
> --
> 2.24.1
>
