> +;; vmlal_lane_s16 intrinsics
> +(define_insn "aarch64_vec_<su>mlal_lane<Qlane>"
> + [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
> + (plus:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "0")
> + (mult:<VWIDE>
> + (ANY_EXTEND:<VWIDE>
> + (match_operand:<VCOND> 2 "register_operand" "w"))
> + (ANY_EXTEND:<VWIDE>
> + (vec_duplicate:<VCOND>
> + (vec_select:<VEL>
> + (match_operand:VDQHS 3 "register_operand" "<vwx>")
> + (parallel [(match_operand:SI 4 "immediate_operand"
> "i")])))))))]
> + "TARGET_SIMD"
> + {
> + operands[4] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[4]));
> + return "<su>mlal\\t%0.<Vwtype>, %2.<Vtype2>, %3.<Vetype>[%4]";
> + }
> + [(set_attr "type" "neon_mla_<Vetype>_scalar_long")]
> +)
> +
The canonical order is to have the (mult ...) first and the register
operand second. (No need to change the operand numbering though,
just swapping them as-is should be fine.)
> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
> index
> ec1b92c5379f7c33446d0ac3556f6358fb7433d3..2f4b553a9a433773b222ce9f0bede3630ff0624c
> 100644
> --- a/gcc/config/aarch64/iterators.md
> +++ b/gcc/config/aarch64/iterators.md
> @@ -980,6 +980,13 @@ (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
> (V4SF "4s") (V2DF "2d")
> (V4HF "4h") (V8HF "8h")])
>
> +;; Map mode to type used in widening multiplies.
> +(define_mode_attr Vtype2 [(V4HI "4h") (V8HI "4h") (V2SI "2s") (V4SI "2s")])
How about Vcondtype, to make it clearer that it's the Vtype associated
with VCOND?
OK with those changes, thanks.
Richard
