Hi all,
second and last patch of the two reworking FPCR and FPSR builtins.
This rework __builtin_aarch64_set_fpcr (unsigned) and
__builtin_aarch64_set_fpsr (unsigned) to emit a read-modify-sequences
as:
mrs x1, fpsr
bfi x1, x0, 0, 32
msr fpsr, x1
This in order to preserve the original high 32 bits of the system
register. Both FPSR and FPCR became 64bit regs with armv8.1.
Bootstrapped on aarch64-linux-gnu, does not introduce regressions.
Regards
Andrea
gcc/ChangeLog:
2020-??-?? Andrea Corallo <andrea.cora...@arm.com>
* config/aarch64/aarch64.md (insv_reg<mode>): Pattern renamed.
(set_fpcr, set_fpsr): Pattern modified for read-modify-write
sequence respecting high 32bit register content.
gcc/testsuite/ChangeLog:
2020-??-?? Andrea Corallo <andrea.cora...@arm.com>
* gcc.target/aarch64/set_fpcr.c: New test.
* gcc.target/aarch64/get_fpcr.c: New test.
* gcc.target/aarch64/set_fpsr.c: New test.
* gcc.target/aarch64/get_fpsr.c: New test.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index b6836710c9c2..b6ee2e1a946e 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -5613,7 +5613,7 @@
operands[3] = force_reg (<MODE>mode, value);
})
-(define_insn "*insv_reg<mode>"
+(define_insn "insv_reg<mode>"
[(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r")
(match_operand 1 "const_int_operand" "n")
(match_operand 2 "const_int_operand" "n"))
@@ -7173,10 +7173,21 @@
(set_attr "type" "multiple")])
;; Write Floating-point Control Register.
-(define_insn "set_fpcr"
- [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] UNSPECV_SET_FPCR)]
+
+(define_expand "set_fpcr"
+ [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
+ UNSPECV_SET_FPCR)]
""
- "msr\\tfpcr, %0"
+ {
+ rtx val32 = simplify_gen_subreg (DImode, operands[0], SImode, 0);
+ /* Read-modify-write sequence. */
+ rtx scratch = gen_reg_rtx (DImode);
+ emit_insn (gen_get_fpcr64 (scratch));
+ emit_insn (gen_insv_regdi (scratch, GEN_INT (32), GEN_INT (0),
+ val32));
+ emit_insn (gen_set_fpcr64 (scratch));
+ DONE;
+ }
[(set_attr "type" "mrs")])
;; Read Floating-point Control Register.
@@ -7188,10 +7199,19 @@
[(set_attr "type" "mrs")])
;; Write Floating-point Status Register.
-(define_insn "set_fpsr"
+(define_expand "set_fpsr"
[(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] UNSPECV_SET_FPSR)]
""
- "msr\\tfpsr, %0"
+ {
+ rtx val32 = simplify_gen_subreg (DImode, operands[0], SImode, 0);
+ /* Read-modify-write sequence. */
+ rtx scratch = gen_reg_rtx (DImode);
+ emit_insn (gen_get_fpsr64 (scratch));
+ emit_insn (gen_insv_regdi (scratch, GEN_INT (32), GEN_INT (0),
+ val32));
+ emit_insn (gen_set_fpsr64 (scratch));
+ DONE;
+ }
[(set_attr "type" "mrs")])
;; Read Floating-point Status Register.
diff --git a/gcc/testsuite/gcc.target/aarch64/get_fpcr.c b/gcc/testsuite/gcc.target/aarch64/get_fpcr.c
new file mode 100644
index 000000000000..f33e70e34cd9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/get_fpcr.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int
+get_fpcr ()
+{
+ return __builtin_aarch64_get_fpcr ();
+}
+
+/* { dg-final { scan-assembler-times "mrs.*fpcr" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/get_fpsr.c b/gcc/testsuite/gcc.target/aarch64/get_fpsr.c
new file mode 100644
index 000000000000..2f7d75637d20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/get_fpsr.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int
+get_fpsr ()
+{
+ return __builtin_aarch64_get_fpsr ();
+}
+
+/* { dg-final { scan-assembler-times "mrs.*fpsr" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/set_fpcr.c b/gcc/testsuite/gcc.target/aarch64/set_fpcr.c
new file mode 100644
index 000000000000..74525981f323
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/set_fpcr.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+set_fpcr (unsigned int x)
+{
+ return __builtin_aarch64_set_fpcr (x);
+}
+
+/* { dg-final { scan-assembler-times "bfi" 1 } } */
+/* { dg-final { scan-assembler-times "mrs.*fpcr" 1 } } */
+/* { dg-final { scan-assembler-times "msr.*fpcr" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/set_fpsr.c b/gcc/testsuite/gcc.target/aarch64/set_fpsr.c
new file mode 100644
index 000000000000..e3e2e631f70c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/set_fpsr.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+set_fpsr (unsigned int x)
+{
+ return __builtin_aarch64_set_fpsr (x);
+}
+
+/* { dg-final { scan-assembler-times "bfi" 1 } } */
+/* { dg-final { scan-assembler-times "mrs.*fpsr" 1 } } */
+/* { dg-final { scan-assembler-times "msr.*fpsr" 1 } } */
