Hi Srinath,
> -----Original Message-----
> From: Srinath Parvathaneni <srinath.parvathan...@arm.com>
> Sent: 18 March 2020 17:18
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
> Subject: [PATCH v2][ARM][GCC][2/5x]: MVE load intrinsics.
>
> Hello Kyrill,
>
> Following patch is the rebased version of v1.
> (version v1) https://gcc.gnu.org/pipermail/gcc-patches/2019-
> November/534338.html
>
> ####
>
> Hello,
>
> This patch supports the following MVE ACLE load intrinsics.
>
> vldrbq_gather_offset_u8, vldrbq_gather_offset_s8, vldrbq_s8, vldrbq_u8,
> vldrbq_gather_offset_u16, vldrbq_gather_offset_s16, vldrbq_s16,
> vldrbq_u16, vldrbq_gather_offset_u32, vldrbq_gather_offset_s32,
> vldrbq_s32, vldrbq_u32, vldrwq_gather_base_s32, vldrwq_gather_base_u32.
>
> Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more
> details.
> [1] https://developer.arm.com/architectures/instruction-sets/simd-
> isas/helium/mve-intrinsics
>
> Regression tested on arm-none-eabi and found no regressions.
>
> Ok for trunk?
Thanks, I've pushed this patch to master.
Kyrill
>
> Thanks,
> Srinath.
>
> gcc/ChangeLog:
>
> 2019-11-01 Andre Vieira <andre.simoesdiasvie...@arm.com>
> Mihail Ionescu <mihail.ione...@arm.com>
> Srinath Parvathaneni <srinath.parvathan...@arm.com>
>
> * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin
> qualifier.
> (LDRGS_QUALIFIERS): Likewise.
> (LDRS_QUALIFIERS): Likewise.
> (LDRU_QUALIFIERS): Likewise.
> (LDRGBS_QUALIFIERS): Likewise.
> (LDRGBU_QUALIFIERS): Likewise.
> * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro.
> (vldrbq_gather_offset_s8): Likewise.
> (vldrbq_s8): Likewise.
> (vldrbq_u8): Likewise.
> (vldrbq_gather_offset_u16): Likewise.
> (vldrbq_gather_offset_s16): Likewise.
> (vldrbq_s16): Likewise.
> (vldrbq_u16): Likewise.
> (vldrbq_gather_offset_u32): Likewise.
> (vldrbq_gather_offset_s32): Likewise.
> (vldrbq_s32): Likewise.
> (vldrbq_u32): Likewise.
> (vldrwq_gather_base_s32): Likewise.
> (vldrwq_gather_base_u32): Likewise.
> (__arm_vldrbq_gather_offset_u8): Define intrinsic.
> (__arm_vldrbq_gather_offset_s8): Likewise.
> (__arm_vldrbq_s8): Likewise.
> (__arm_vldrbq_u8): Likewise.
> (__arm_vldrbq_gather_offset_u16): Likewise.
> (__arm_vldrbq_gather_offset_s16): Likewise.
> (__arm_vldrbq_s16): Likewise.
> (__arm_vldrbq_u16): Likewise.
> (__arm_vldrbq_gather_offset_u32): Likewise.
> (__arm_vldrbq_gather_offset_s32): Likewise.
> (__arm_vldrbq_s32): Likewise.
> (__arm_vldrbq_u32): Likewise.
> (__arm_vldrwq_gather_base_s32): Likewise.
> (__arm_vldrwq_gather_base_u32): Likewise.
> (vldrbq_gather_offset): Define polymorphic variant.
> * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use
> builtin
> qualifier.
> (LDRGS_QUALIFIERS): Likewise.
> (LDRS_QUALIFIERS): Likewise.
> (LDRU_QUALIFIERS): Likewise.
> (LDRGBS_QUALIFIERS): Likewise.
> (LDRGBU_QUALIFIERS): Likewise.
> * config/arm/mve.md (VLDRBGOQ): Define iterator.
> (VLDRBQ): Likewise.
> (VLDRWGBQ): Likewise.
> (mve_vldrbq_gather_offset_<supf><mode>): Define RTL pattern.
> (mve_vldrbq_<supf><mode>): Likewise.
> (mve_vldrwq_gather_base_<supf>v4si): Likewise.
>
> gcc/testsuite/ChangeLog:
>
> 2019-11-01 Andre Vieira <andre.simoesdiasvie...@arm.com>
> Mihail Ionescu <mihail.ione...@arm.com>
> Srinath Parvathaneni <srinath.parvathan...@arm.com>
>
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c: New
> test.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_s16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c: Likewise.
>
>
> ############### Attachment also inlined for ease of reply
> ###############
>
>
> diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
> index
> b285f074285116ce621e324b644d43efb6538b9d..aced55f52d317e8deafdc6a6
> 804db3b80c00fd80 100644
> --- a/gcc/config/arm/arm-builtins.c
> +++ b/gcc/config/arm/arm-builtins.c
> @@ -612,6 +612,36 @@ arm_strsbu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> qualifier_unsigned};
> #define STRSBU_QUALIFIERS (arm_strsbu_qualifiers)
>
> +static enum arm_type_qualifiers
> +arm_ldrgu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> + = { qualifier_unsigned, qualifier_pointer, qualifier_unsigned};
> +#define LDRGU_QUALIFIERS (arm_ldrgu_qualifiers)
> +
> +static enum arm_type_qualifiers
> +arm_ldrgs_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> + = { qualifier_none, qualifier_pointer, qualifier_unsigned}; #define
> +LDRGS_QUALIFIERS (arm_ldrgs_qualifiers)
> +
> +static enum arm_type_qualifiers
> +arm_ldrs_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> + = { qualifier_none, qualifier_pointer}; #define LDRS_QUALIFIERS
> +(arm_ldrs_qualifiers)
> +
> +static enum arm_type_qualifiers
> +arm_ldru_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> + = { qualifier_unsigned, qualifier_pointer}; #define LDRU_QUALIFIERS
> +(arm_ldru_qualifiers)
> +
> +static enum arm_type_qualifiers
> +arm_ldrgbs_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> + = { qualifier_none, qualifier_unsigned, qualifier_immediate}; #define
> +LDRGBS_QUALIFIERS (arm_ldrgbs_qualifiers)
> +
> +static enum arm_type_qualifiers
> +arm_ldrgbu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> + = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate};
> +#define LDRGBU_QUALIFIERS (arm_ldrgbu_qualifiers)
> +
> /* End of Qualifier for MVE builtins. */
>
> /* void ([T element type] *, T, immediate). */ diff --git
> a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index
> 019e907c6dc0b0572b7597f9e82b7ad8e6331bef..c2c195a9270e976c21d8d0a
> 5941f85dd2bdd9e9d 100644
> --- a/gcc/config/arm/arm_mve.h
> +++ b/gcc/config/arm/arm_mve.h
> @@ -1716,6 +1716,20 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t;
> #define vstrbq_scatter_offset_s32( __base, __offset, __value)
> __arm_vstrbq_scatter_offset_s32( __base, __offset, __value) #define
> vstrwq_scatter_base_s32(__addr, __offset, __value)
> __arm_vstrwq_scatter_base_s32(__addr, __offset, __value) #define
> vstrwq_scatter_base_u32(__addr, __offset, __value)
> __arm_vstrwq_scatter_base_u32(__addr, __offset, __value)
> +#define vldrbq_gather_offset_u8(__base, __offset)
> +__arm_vldrbq_gather_offset_u8(__base, __offset) #define
> +vldrbq_gather_offset_s8(__base, __offset)
> +__arm_vldrbq_gather_offset_s8(__base, __offset) #define
> +vldrbq_s8(__base) __arm_vldrbq_s8(__base) #define vldrbq_u8(__base)
> +__arm_vldrbq_u8(__base) #define vldrbq_gather_offset_u16(__base,
> +__offset) __arm_vldrbq_gather_offset_u16(__base, __offset) #define
> +vldrbq_gather_offset_s16(__base, __offset)
> +__arm_vldrbq_gather_offset_s16(__base, __offset) #define
> +vldrbq_s16(__base) __arm_vldrbq_s16(__base) #define vldrbq_u16(__base)
> +__arm_vldrbq_u16(__base) #define vldrbq_gather_offset_u32(__base,
> +__offset) __arm_vldrbq_gather_offset_u32(__base, __offset) #define
> +vldrbq_gather_offset_s32(__base, __offset)
> +__arm_vldrbq_gather_offset_s32(__base, __offset) #define
> +vldrbq_s32(__base) __arm_vldrbq_s32(__base) #define vldrbq_u32(__base)
> +__arm_vldrbq_u32(__base) #define vldrwq_gather_base_s32(__addr,
> +__offset) __arm_vldrwq_gather_base_s32(__addr, __offset) #define
> +vldrwq_gather_base_u32(__addr, __offset)
> +__arm_vldrwq_gather_base_u32(__addr, __offset)
> #endif
>
> __extension__ extern __inline void
> @@ -11106,6 +11120,105 @@ __arm_vstrwq_scatter_base_u32 (uint32x4_t
> __addr, const int __offset, uint32x4_t {
> __builtin_mve_vstrwq_scatter_base_uv4si (__addr, __offset, __value); }
> +
> +__extension__ extern __inline uint8x16_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vldrbq_gather_offset_u8 (uint8_t const * __base, uint8x16_t
> +__offset) {
> + return __builtin_mve_vldrbq_gather_offset_uv16qi ((__builtin_neon_qi
> +*) __base, __offset); }
> +
> +__extension__ extern __inline int8x16_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vldrbq_gather_offset_s8 (int8_t const * __base, uint8x16_t
> +__offset) {
> + return __builtin_mve_vldrbq_gather_offset_sv16qi ((__builtin_neon_qi
> +*) __base, __offset); }
> +
> +__extension__ extern __inline int8x16_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vldrbq_s8 (int8_t const * __base) {
> + return __builtin_mve_vldrbq_sv16qi ((__builtin_neon_qi *) __base); }
> +
> +__extension__ extern __inline uint8x16_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vldrbq_u8 (uint8_t const * __base) {
> + return __builtin_mve_vldrbq_uv16qi ((__builtin_neon_qi *) __base); }
> +
> +__extension__ extern __inline uint16x8_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vldrbq_gather_offset_u16 (uint8_t const * __base, uint16x8_t
> +__offset) {
> + return __builtin_mve_vldrbq_gather_offset_uv8hi ((__builtin_neon_qi
> +*) __base, __offset); }
> +
> +__extension__ extern __inline int16x8_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vldrbq_gather_offset_s16 (int8_t const * __base, uint16x8_t
> +__offset) {
> + return __builtin_mve_vldrbq_gather_offset_sv8hi ((__builtin_neon_qi
> +*) __base, __offset); }
> +
> +__extension__ extern __inline int16x8_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vldrbq_s16 (int8_t const * __base) {
> + return __builtin_mve_vldrbq_sv8hi ((__builtin_neon_qi *) __base); }
> +
> +__extension__ extern __inline uint16x8_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vldrbq_u16 (uint8_t const * __base) {
> + return __builtin_mve_vldrbq_uv8hi ((__builtin_neon_qi *) __base); }
> +
> +__extension__ extern __inline uint32x4_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vldrbq_gather_offset_u32 (uint8_t const * __base, uint32x4_t
> +__offset) {
> + return __builtin_mve_vldrbq_gather_offset_uv4si ((__builtin_neon_qi
> +*) __base, __offset); }
> +
> +__extension__ extern __inline int32x4_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vldrbq_gather_offset_s32 (int8_t const * __base, uint32x4_t
> +__offset) {
> + return __builtin_mve_vldrbq_gather_offset_sv4si ((__builtin_neon_qi
> +*) __base, __offset); }
> +
> +__extension__ extern __inline int32x4_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vldrbq_s32 (int8_t const * __base) {
> + return __builtin_mve_vldrbq_sv4si ((__builtin_neon_qi *) __base); }
> +
> +__extension__ extern __inline uint32x4_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vldrbq_u32 (uint8_t const * __base) {
> + return __builtin_mve_vldrbq_uv4si ((__builtin_neon_qi *) __base); }
> +
> +__extension__ extern __inline int32x4_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vldrwq_gather_base_s32 (uint32x4_t __addr, const int __offset) {
> + return __builtin_mve_vldrwq_gather_base_sv4si (__addr, __offset); }
> +
> +__extension__ extern __inline uint32x4_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vldrwq_gather_base_u32 (uint32x4_t __addr, const int __offset) {
> + return __builtin_mve_vldrwq_gather_base_uv4si (__addr, __offset); }
> +
> #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
>
> __extension__ extern __inline void
> @@ -17770,6 +17883,57 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_s32(p0,
> p1, __ARM_mve_coerce(__p2, int32x4_t)), \
> int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_u32(p0,
> p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
>
> +#define vldrbq_gather_offset(p0,p1) __arm_vldrbq_gather_offset(p0,p1)
> +#define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0);
> +\
> + __typeof(p1) __p1 = (p1); \
> + _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> +\
> + int
> (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint8x16_t]:
> +__arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce(__p0, int8_t const *),
> +__ARM_mve_coerce(__p1, uint8x16_t)), \
> + int
> (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint16x8_t]:
> +__arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce(__p0, int8_t const
> *),
> +__ARM_mve_coerce(__p1, uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint32x4_t]:
> +__arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce(__p0, int8_t const
> *),
> +__ARM_mve_coerce(__p1, uint32x4_t)), \
> + int
> (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint8x16_t]:
> +__arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce(__p0, uint8_t const
> *),
> +__ARM_mve_coerce(__p1, uint8x16_t)), \
> + int
> (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint16x8_t]:
> +__arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce(__p0, uint8_t const
> +*), __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint32x4_t]:
> +__arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce(__p0, uint8_t const
> +*), __ARM_mve_coerce(__p1, uint32x4_t)));})
> +
> +#define vstrbq_p(p0,p1,p2) __arm_vstrbq_p(p0,p1,p2) #define
> +__arm_vstrbq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
> + __typeof(p1) __p1 = (p1); \
> + _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> +\
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]:
> +__arm_vstrbq_p_s8 (__ARM_mve_coerce(__p0, int8_t *),
> +__ARM_mve_coerce(__p1, int8x16_t), p2), \
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]:
> +__arm_vstrbq_p_s16 (__ARM_mve_coerce(__p0, int8_t *),
> +__ARM_mve_coerce(__p1, int16x8_t), p2), \
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]:
> +__arm_vstrbq_p_s32 (__ARM_mve_coerce(__p0, int8_t *),
> +__ARM_mve_coerce(__p1, int32x4_t), p2), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> +__arm_vstrbq_p_u8 (__ARM_mve_coerce(__p0, uint8_t *),
> +__ARM_mve_coerce(__p1, uint8x16_t), p2), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]:
> +__arm_vstrbq_p_u16 (__ARM_mve_coerce(__p0, uint8_t *),
> +__ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]:
> +__arm_vstrbq_p_u32 (__ARM_mve_coerce(__p0, uint8_t *),
> +__ARM_mve_coerce(__p1, uint32x4_t), p2));})
> +
> +#define vstrbq_scatter_offset_p(p0,p1,p2,p3)
> +__arm_vstrbq_scatter_offset_p(p0,p1,p2,p3)
> +#define __arm_vstrbq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0
> += (p0); \
> + __typeof(p1) __p1 = (p1); \
> + __typeof(p2) __p2 = (p2); \
> + _Generic( (int
> +(*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_ty
> peid(__
> +p2)])0, \
> + int
> +(*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_
> mve_typ
> +e_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8
> (__ARM_mve_coerce(__p0,
> +int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2,
> +int8x16_t), p3), \
> + int
> +(*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_typ
> +e_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16
> (__ARM_mve_coerce(__p0,
> +int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2,
> +int16x8_t), p3), \
> + int
> +(*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_typ
> +e_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32
> (__ARM_mve_coerce(__p0,
> +int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2,
> +int32x4_t), p3), \
> + int
> +(*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_
> mve_ty
> +pe_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8
> +(__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint8x16_t),
> +__ARM_mve_coerce(__p2, uint8x16_t), p3), \
> + int
> +(*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_ty
> +pe_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16
> +(__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint16x8_t),
> +__ARM_mve_coerce(__p2, uint16x8_t), p3), \
> + int
> +(*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_ty
> +pe_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32
> +(__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1,
> uint32x4_t),
> +__ARM_mve_coerce(__p2, uint32x4_t), p3));})
> +
> +#define vstrwq_scatter_base_p(p0,p1,p2,p3)
> +__arm_vstrwq_scatter_base_p(p0,p1,p2,p3)
> +#define __arm_vstrwq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 =
> +(p2); \
> + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
> + int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_p_s32
> +(p0, p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
> + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32
> +(p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
> +
> +#define vldrbq_gather_offset_z(p0,p1,p2)
> +__arm_vldrbq_gather_offset_z(p0,p1,p2)
> +#define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 =
> +(p0); \
> + __typeof(p1) __p1 = (p1); \
> + _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> +\
> + int
> (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint8x16_t]:
> +__arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce(__p0, int8_t const
> +*), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> + int
> (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint16x8_t]:
> +__arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce(__p0, int8_t const
> +*), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int
> (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint32x4_t]:
> +__arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce(__p0, int8_t const
> +*), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
> + int
> (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint8x16_t]:
> +__arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce(__p0, uint8_t
> const
> +*), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
> + int
> (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint16x8_t]:
> +__arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce(__p0, uint8_t
> const
> +*), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
> + int
> (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint32x4_t]:
> +__arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint8_t
> const
> +*), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
> +
> #endif /* MVE Integer. */
>
> #define vqrdmlahq_m(p0,p1,p2,p3) __arm_vqrdmlahq_m(p0,p1,p2,p3) @@
> -18497,6 +18661,17 @@ extern void *__ARM_undef;
> int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t][__ARM_m
> ve_type_uint8x16_t]: __arm_vmullbq_poly_m_p8
> (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1,
> uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
> int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_uint16x8_t]: __arm_vmullbq_poly_m_p16
> (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1,
> uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3));})
>
> +#define vldrbq_gather_offset(p0,p1) __arm_vldrbq_gather_offset(p0,p1)
> +#define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0);
> +\
> + __typeof(p1) __p1 = (p1); \
> + _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> +\
> + int
> (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint8x16_t]:
> +__arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce(__p0, int8_t const *),
> +__ARM_mve_coerce(__p1, uint8x16_t)), \
> + int
> (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint16x8_t]:
> +__arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce(__p0, int8_t const
> *),
> +__ARM_mve_coerce(__p1, uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint32x4_t]:
> +__arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce(__p0, int8_t const
> *),
> +__ARM_mve_coerce(__p1, uint32x4_t)), \
> + int
> (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint8x16_t]:
> +__arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce(__p0, uint8_t const
> *),
> +__ARM_mve_coerce(__p1, uint8x16_t)), \
> + int
> (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint16x8_t]:
> +__arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce(__p0, uint8_t const
> +*), __ARM_mve_coerce(__p1, uint16x8_t)), \
> + int
> (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint32x4_t]:
> +__arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce(__p0, uint8_t const
> +*), __ARM_mve_coerce(__p1, uint32x4_t)));})
> +
> #ifdef __cplusplus
> }
> #endif
> diff --git a/gcc/config/arm/arm_mve_builtins.def
> b/gcc/config/arm/arm_mve_builtins.def
> index
> 2c675240984ac3aa64faf6a9199441c29528c704..f6d0fec2fb4795d452ecd5478
> 577d564a384220b 100644
> --- a/gcc/config/arm/arm_mve_builtins.def
> +++ b/gcc/config/arm/arm_mve_builtins.def
> @@ -691,3 +691,9 @@ VAR3 (STRSS, vstrbq_scatter_offset_s, v16qi, v8hi,
> v4si)
> VAR3 (STRSU, vstrbq_scatter_offset_u, v16qi, v8hi, v4si)
> VAR1 (STRSBS, vstrwq_scatter_base_s, v4si)
> VAR1 (STRSBU, vstrwq_scatter_base_u, v4si)
> +VAR3 (LDRGU, vldrbq_gather_offset_u, v16qi, v8hi, v4si)
> +VAR3 (LDRGS, vldrbq_gather_offset_s, v16qi, v8hi, v4si)
> +VAR3 (LDRS, vldrbq_s, v16qi, v8hi, v4si)
> +VAR3 (LDRU, vldrbq_u, v16qi, v8hi, v4si)
> +VAR1 (LDRGBS, vldrwq_gather_base_s, v4si)
> +VAR1 (LDRGBU, vldrwq_gather_base_u, v4si)
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index
> 3d0a1725d416aa3e465de9409977394d06c19897..be1b9faee7f94124ecd6f37c
> fff55003d162aee5 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -192,7 +192,8 @@
> VCMULQ_ROT270_M_F VCMULQ_ROT90_M_F
> VFMAQ_M_F
> VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F
> VMAXNMQ_M_F
> VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S
> VSTRWQSB_U
> - VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U])
> + VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U
> VLDRBQGO_S
> + VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S
> VLDRWQGB_U])
>
> (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
> (V8HF "V8HI") (V4SF "V4SI")])
> @@ -345,7 +346,9 @@
> (VMLALDAVAXQ_P_S "s") (VMLALDAVAXQ_P_U "u")
> (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u")
> (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s")
> - (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")])
> + (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")
> + (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s")
> + (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")])
>
> (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
> (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
> @@ -569,6 +572,9 @@ (define_int_iterator VSTRWSBQ [VSTRWQSB_S
> VSTRWQSB_U]) (define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U])
> (define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U])
> +(define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U])
> +(define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U]) (define_int_iterator
> +VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U])
>
> (define_insn "*mve_mov<mode>"
> [(set (match_operand:MVE_types 0 "nonimmediate_operand"
> "=w,w,r,w,w,r,w,Us") @@ -8009,3 +8015,65 @@
> return "";
> }
> [(set_attr "length" "4")])
> +
> +;;
> +;; [vldrbq_gather_offset_s vldrbq_gather_offset_u] ;; (define_insn
> +"mve_vldrbq_gather_offset_<supf><mode>"
> + [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
> + (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1
> "memory_operand" "Us")
> + (match_operand:MVE_2 2 "s_register_operand" "w")]
> + VLDRBGOQ))
> + ]
> + "TARGET_HAVE_MVE"
> +{
> + rtx ops[3];
> + ops[0] = operands[0];
> + ops[1] = operands[1];
> + ops[2] = operands[2];
> + if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
> + output_asm_insn ("vldrb.u8\t%q0, [%m1, %q2]",ops);
> + else
> + output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
> + return "";
> +}
> + [(set_attr "length" "4")])
> +
> +;;
> +;; [vldrbq_s vldrbq_u]
> +;;
> +(define_insn "mve_vldrbq_<supf><mode>"
> + [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
> + (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1
> "memory_operand" "Us")]
> + VLDRBQ))
> + ]
> + "TARGET_HAVE_MVE"
> +{
> + rtx ops[2];
> + int regno = REGNO (operands[0]);
> + ops[0] = gen_rtx_REG (TImode, regno);
> + ops[1] = operands[1];
> + output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, %E1",ops);
> + return "";
> +}
> + [(set_attr "length" "4")])
> +
> +;;
> +;; [vldrwq_gather_base_s vldrwq_gather_base_u] ;; (define_insn
> +"mve_vldrwq_gather_base_<supf>v4si"
> + [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
> + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
> + (match_operand:SI 2 "immediate_operand" "i")]
> + VLDRWGBQ))
> + ]
> + "TARGET_HAVE_MVE"
> +{
> + rtx ops[3];
> + ops[0] = operands[0];
> + ops[1] = operands[1];
> + ops[2] = operands[2];
> + output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops);
> + return "";
> +}
> + [(set_attr "length" "4")])
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..d945c6576a01029cff3a94b
> 6df851a9c6124bd77
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s
> +++ 16.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +int16x8_t
> +foo (int8_t const * base, uint16x8_t offset) {
> + return vldrbq_gather_offset_s16 (base, offset); }
> +
> +/* { dg-final { scan-assembler "vldrb.s16" } } */
> +
> +int16x8_t
> +foo1 (int8_t const * base, uint16x8_t offset) {
> + return vldrbq_gather_offset (base, offset); }
> +
> +/* { dg-final { scan-assembler "vldrb.s16" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..de7c681b6749ffbdd672855
> 3ef165da54c007783
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s
> +++ 32.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +int32x4_t
> +foo (int8_t const * base, uint32x4_t offset) {
> + return vldrbq_gather_offset_s32 (base, offset); }
> +
> +/* { dg-final { scan-assembler "vldrb.s32" } } */
> +
> +int32x4_t
> +foo1 (int8_t const * base, uint32x4_t offset) {
> + return vldrbq_gather_offset (base, offset); }
> +
> +/* { dg-final { scan-assembler "vldrb.s32" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..6e85ec2eb6bfc0d89b0b430
> 8565eed3122421d22
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s
> +++ 8.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +int8x16_t
> +foo (int8_t const * base, uint8x16_t offset) {
> + return vldrbq_gather_offset_s8 (base, offset); }
> +
> +/* { dg-final { scan-assembler "vldrb.u8" } } */
> +
> +int8x16_t
> +foo1 (int8_t const * base, uint8x16_t offset) {
> + return vldrbq_gather_offset (base, offset); }
> +
> +/* { dg-final { scan-assembler "vldrb.u8" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..d093cd32a723bd95033f669
> c4cf4b6bcdf6c1fa3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u
> +++ 16.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +uint16x8_t
> +foo (uint8_t const * base, uint16x8_t offset) {
> + return vldrbq_gather_offset_u16 (base, offset); }
> +
> +/* { dg-final { scan-assembler "vldrb.u16" } } */
> +
> +uint16x8_t
> +foo1 (uint8_t const * base, uint16x8_t offset) {
> + return vldrbq_gather_offset (base, offset); }
> +
> +/* { dg-final { scan-assembler "vldrb.u16" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..671b3a1e92659df2ee58fe2
> 88efbffdcda57e10f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u
> +++ 32.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +uint32x4_t
> +foo (uint8_t const * base, uint32x4_t offset) {
> + return vldrbq_gather_offset_u32 (base, offset); }
> +
> +/* { dg-final { scan-assembler "vldrb.u32" } } */
> +
> +uint32x4_t
> +foo1 (uint8_t const * base, uint32x4_t offset) {
> + return vldrbq_gather_offset (base, offset); }
> +
> +/* { dg-final { scan-assembler "vldrb.u32" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..57c086e6ef5edd5cbd3cc5f8
> 79557a037deac2ab
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u
> +++ 8.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +uint8x16_t
> +foo (uint8_t const * base, uint8x16_t offset) {
> + return vldrbq_gather_offset_u8 (base, offset); }
> +
> +/* { dg-final { scan-assembler "vldrb.u8" } } */
> +
> +uint8x16_t
> +foo1 (uint8_t const * base, uint8x16_t offset) {
> + return vldrbq_gather_offset (base, offset); }
> +
> +/* { dg-final { scan-assembler "vldrb.u8" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..695fc17535f4e3a1acfd6a10
> 4e560023712fd5b4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +int16x8_t
> +foo (int8_t const * base)
> +{
> + return vldrbq_s16 (base);
> +}
> +
> +/* { dg-final { scan-assembler "vldrb.s16" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..22ac325d15cccca9cff4e619
> bf6c04472a34d1aa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +int32x4_t
> +foo (int8_t const * base)
> +{
> + return vldrbq_s32 (base);
> +}
> +
> +/* { dg-final { scan-assembler "vldrb.s32" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..437639cc966341a3eb4ff2cb
> 0282bffffcb10ca8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +int8x16_t
> +foo (int8_t const * base)
> +{
> + return vldrbq_s8 (base);
> +}
> +
> +/* { dg-final { scan-assembler "vldrb.s8" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..2a48af17a90798201921c83
> af123c829717142a1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +uint16x8_t
> +foo (uint8_t const * base)
> +{
> + return vldrbq_u16 (base);
> +}
> +
> +/* { dg-final { scan-assembler "vldrb.u16" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..ef37295633015b071fddf89
> d2a5e335c1a26fa2c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +uint32x4_t
> +foo (uint8_t const * base)
> +{
> + return vldrbq_u32 (base);
> +}
> +
> +/* { dg-final { scan-assembler "vldrb.u32" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..7366faa98a2ecd337c2ec3bf
> 13a7a3a1b104b503
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +uint8x16_t
> +foo (uint8_t const * base)
> +{
> + return vldrbq_u8 (base);
> +}
> +
> +/* { dg-final { scan-assembler "vldrb.u8" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..a9a695dc593a9381959a777
> 6dcc9704d826c9978
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32
> +++ .c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +int32x4_t
> +foo (uint32x4_t addr)
> +{
> + return vldrwq_gather_base_s32 (addr, 4); }
> +
> +/* { dg-final { scan-assembler "vldrw.u32" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..8c2b541bda2ddb7b00b4aa
> 11acf0876085235617
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32
> +++ .c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +uint32x4_t
> +foo (uint32x4_t addr)
> +{
> + return vldrwq_gather_base_u32 (addr, 4); }
> +
> +/* { dg-final { scan-assembler "vldrw.u32" } } */
