On 2020/3/27 22:33, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Mar 26, 2020 at 05:06:43AM -0500, luo...@linux.ibm.com wrote:
>> Remove split code from add<mode>3 to allow a later pass to split.
>> This allows later logic to hoist out constant load in add instructions.
>> In loop, lis+ori could be hoisted out to improve performance compared with
>> previous addis+addi (About 15% on typical case), weak point is
>> one more register is used and one more instruction is generated. i.e.:
>>
>> addis 3,3,0x8765
>> addi 3,3,0x4321
>>
>> =>
>>
>> lis 9,0x8765
>> ori 9,9,0x4321
>> add 3,3,9
>
> What does it do overall? Say, to SPEC. What does it do to execution
> time, and what does it do to binary size?
>
> Do we want something later in the RTL pipeline to make "addi"s etc. again?
>
>> 2020-03-26 Xiong Hu Luo <luo...@linux.ibm.com>
>>
>> * config/rs6000/rs6000.md (add<mode>3): Remove split code, move constant
>> to temp register before add.
>
> This should not be indented, so just:
> * config/rs6000/rs6000.md (add<mode>3): Remove split code, move constant
> to temp register before add.
>
> We have six separate add<mode>3 patterns (three of those are in rs6000.md,
> too). You can write something like
> (add<mode>3 for SDI):
> to show which iterator (or mode) this one is for. This is helpful with
> any <mode> or <code> or the like, even if there (currently) is only one
> pattern you could mean.
>
Thanks, it is necessary to re-enable split add as some later RTL passes like
final will
still need generate addis+addi (case: g++.dg/opt/thunk1.C ).
Update the patch as below:
[PATCH] rs6000: Don't split constant operator add before reload, move to temp
register for future optimization
Don't split code from add<mode>3 for SDI to allow a later pass to split.
This allows later logic to hoist out constant load in add instructions.
In loop, lis+ori could be hoisted out to improve performance compared with
previous addis+addi (About 15% on typical case), weak point is
one more register is used and one more instruction is generated. i.e.:
addis 3,3,0x8765
addi 3,3,0x4321
=>
lis 9,0x8765
ori 9,9,0x4321
add 3,3,9
No obvious performance and binary size change to SPEC2017.
gcc/ChangeLog:
2020-03-30 Xiong Hu Luo <luo...@linux.ibm.com>
* config/rs6000/rs6000.md (add<mode>3 for SDI): Don't split before
reload,
move constant to temp register for add.
gcc/testsuite/ChangeLog:
2020-03-26 Xiong Hu Luo <luo...@linux.ibm.com>
* gcc.target/powerpc/add-const.c: New.
---
gcc/config/rs6000/rs6000.md | 51 +++++++++-----------
gcc/testsuite/gcc.target/powerpc/add-const.c | 18 +++++++
2 files changed, 42 insertions(+), 27 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/add-const.c
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index ad88b6783af..76af3d5b1d9 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1729,34 +1729,31 @@ (define_expand "add<mode>3"
if (CONST_INT_P (operands[2]) && !add_operand (operands[2], <MODE>mode))
{
- rtx tmp = ((!can_create_pseudo_p ()
- || rtx_equal_p (operands[0], operands[1]))
- ? operands[0] : gen_reg_rtx (<MODE>mode));
-
- /* Adding a constant to r0 is not a valid insn, so use a different
- strategy in that case. */
- if (reg_or_subregno (operands[1]) == 0 || reg_or_subregno (tmp) == 0)
- {
- if (operands[0] == operands[1])
- FAIL;
- rs6000_emit_move (operands[0], operands[2], <MODE>mode);
- emit_insn (gen_add<mode>3 (operands[0], operands[1], operands[0]));
- DONE;
- }
-
- HOST_WIDE_INT val = INTVAL (operands[2]);
- HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
- HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
-
- if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
- FAIL;
+ if (can_create_pseudo_p ())
+ {
+ rtx tmp = rtx_equal_p (operands[0], operands[1])
+ ? operands[0] : gen_reg_rtx (<MODE>mode);
- /* The ordering here is important for the prolog expander.
- When space is allocated from the stack, adding 'low' first may
- produce a temporary deallocation (which would be bad). */
- emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
- emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
- DONE;
+ rs6000_emit_move (tmp, operands[2], <MODE>mode);
+ emit_insn (gen_add<mode>3 (operands[0], operands[1], tmp));
+ DONE;
+ }
+ else
+ {
+ HOST_WIDE_INT val = INTVAL (operands[2]);
+ HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
+ HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
+
+ if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
+ FAIL;
+
+ /* The ordering here is important for the prolog expander.
+ When space is allocated from the stack, adding 'low' first may
+ produce a temporary deallocation (which would be bad). */
+ emit_insn (gen_add<mode>3 (operands[0], operands[1], GEN_INT (rest)));
+ emit_insn (gen_add<mode>3 (operands[0], operands[0], GEN_INT (low)));
+ DONE;
+ }
}
})
diff --git a/gcc/testsuite/gcc.target/powerpc/add-const.c
b/gcc/testsuite/gcc.target/powerpc/add-const.c
new file mode 100644
index 00000000000..e1007247b32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/add-const.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target { lp64 } } } */
+/* { dg-options "-O3 -fno-unroll-loops" } */
+
+/* Ensure the lis,ori are generated, which indicates they have
+ been hoisted outside of the loop. */
+
+typedef unsigned long ulong;
+ulong
+foo (ulong n, ulong h)
+{
+ int i;
+ for (i = 0; i < n; i++)
+ h = ((h + 8) | h) + 0x87654321;
+ return h;
+}
+
+/* { dg-final { scan-assembler-times {\mlis\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mori\M} 1 } } */
--
2.21.0.777.g83232e3864
