On 4/7/20 4:58 PM, Segher Boessenkool wrote:
>> I wonder if it would be helpful to have
>>
>> (uoverflow_plus x y carry)
>> (soverflow_plus x y carry)
>>
>> etc.
>
> Those have three operands, which is nasty to express.
How so? It's a perfectly natural operation.
> On rs6000 we have the carry bit as a separate register (it really is
> only one bit, XER[CA], but in GCC we model it as a separate register).
> We handle it as a fixed register (there is only one, and saving and
> restoring it is relatively expensive, so this worked out the best).
As for most platforms, more or less.
> Still, in the patterns (for insns like "adde") that take both a carry
> input and have it as output, the expression for the carry output but
> already the one for the GPR output become so unwieldy that nothing
> can properly work with it. So, in the end, I have all such insns that
> take a carry input just clobber their carry output. This works great!
Sure, right up until the point when you want to actually *use* that carry
output. Which is exactly what we're talking about here.
> Expressing the carry setting for insns that do not take a carry in is
> much easier. You get somewhat different patterns for various
> immediate inputs, but that is all.
It's not horrible, but it's certainly verbose. If we add a shorthand for that
common operation, so much the better.
I would not expect optimizers to take a collection of inputs and introduce this
rtx code, but only operate with it when the backend emits it.
>> This does have the advantage of avoiding the extensions, so that constants
>> can
>> be retained in the original mode.
>
> But it won't ever survive simplification; or, it will be in the way of
> simplification.
How so?
It's clear that
(set (reg:CC_C flags)
(uoverflow_plus:CC_C
(reg:SI x)
(const_int 0)
(const_int 0)))
cannot overflow. Thus this expression as a whole would, in combination with
the user of the CC_MODE, e.g.
(set (reg:SI y) (ne:SI (reg:CC_C flags) (const_int 0))
fold to
(set (reg:SI y) (ne:SI (const_int 0) (const_int 0))
to
(set (reg:SI y) (const_int 0))
just like any other (compare) + (condition) pair.
I don't see why this new rtx code is any more difficult than ones that we have
already.
>> Though of course if we go this way, there will be incentive to add
>> <s,u>overflow codes for all __builtin_*_overflow_p.
>
> Yeah, eww. And where will it stop? What muladd insns should we have
> special RTL codes for, for the high part?
Well, we don't have overflow builtins for muladd yet. Only plus, minus, and
mul. Only x86 and s390x have insns to support overflow from mul without also
computing the highpart.
But add/sub-with-carry are *very* common operations. As are add/sub-with-carry
with signed overflow into flags. It would be nice to make that as simple as
possible across all targets.
r~
