On Sat, Apr 11, 2020 at 02:48:22PM -0700, H.J. Lu via Gcc-patches wrote:
> Even though ix86_hard_regno_mode_ok doesn't allow xmm16-xmm31 nor
> ymm16-ymm31 in 128/256 bit modes when AVX512VL is disabled, reload
> can still generate reg to reg moves with xmm16-xmm31 and ymm16-ymm31
> in 128/256 bit modes. Remove mode size check in ix86_get_ssemov.
Looking at the testcase, LRA doesn't have good choices,
(define_insn ("*avx512f_gatherdiv16si")
[
(set (match_operand:V16SI 0 ("register_operand") ("=&v"))
(unspec:V16SI [
(match_operand:V8SI 1 ("register_operand") ("0"))
...
so if the output is chosen to be zmm16+, then LRA is required to stick
a V8SI pseudo into that register, even when ix86_hard_regno_mode_ok
isn't ok with that.
Unless we changed all the patterns with such issues (i.e. where a
128-bit/256-bit operand uses matching constraint to 512-bit one with
v) so that it uses just x on the matching operand unless avx512vl.
Before your changes, we would just emit the *mov<mode>_internal even in
those cases, so your change matches what we used to do.
>
> gcc/
>
> PR target/94561
> * config/i386/i386.c (ix86_get_ssemov): Remove mode size check.
>
> gcc/testsuite/
>
> PR target/94561
> * gcc.target/i386/pr94561.c: New test.
Ok.
Jakub
