On 5/8/20 2:00 PM, Segher Boessenkool wrote:
On Thu, May 07, 2020 at 09:11:32PM -0500, Bill Schmidt wrote:
From: Kelvin Nilsen <kel...@gcc.gnu.org>
Add support for new vclzdm and vctzdm vector instructions that
count leading and trailing zeros under control of a mask.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this okay for master?
(On what CPU / with what -mcpu= settings?)
Sorry for lack of clarity. All of these patches are tested on a P9.
The test cases have appropriate -mcpu= settings. Those run-time tests
requiring an architecture that supports these instructions show up as
UNSUPPORTED in that configuration, of course. My understanding is that
Kelvin ran these tests on a simulator, but I do not know that for
certain and haven't repeated those tests. Any problems that may have
crept in since then will get caught at such time that hardware is available.
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 6b1d987913c..5ef4889ba55 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -160,6 +160,8 @@ (define_c_enum "unspec"
UNSPEC_BCD_OVERFLOW
UNSPEC_VRLMI
UNSPEC_VRLNM
+ UNSPEC_VCLZDM
+ UNSPEC_VCTZDM
Hrm, this can actually be the same unspecs as used for the GPR version,
the mode will make the difference already? Doesn't really matter of
course.
True!
(This needs an unspec because it isn't viable to describe in RTL what
this op does -- it is not an AND with the mask and then a count, the
masked-out bits are actually skipped for the count).
Looks fine to me, thanks,
Thanks,
Bill
Segher
