On 6/10/20 10:42 AM, Jakub Jelinek wrote:
E.g. we just shouldn't reuse
MEMs (even after adjusting them) from different indirection levels because
we risk some attributes (alias set, MEM_EXPR, whatever else) will stay
around from the different indirection level.
All right, what about the updated patch? I must confess that RTL instruction
emission is not my strength.
Martin
>From 16e46a532c059930887bc30f82c3054a75a5a56d Mon Sep 17 00:00:00 2001
From: Martin Liska <mli...@suse.cz>
Date: Tue, 19 May 2020 16:57:56 +0200
Subject: [PATCH] Add missing store in emission of asan_stack_free.
gcc/ChangeLog:
2020-05-19 Martin Liska <mli...@suse.cz>
PR sanitizer/94910
* asan.c (asan_emit_stack_protection): Emit
also **SavedFlagPtr(FakeStack) = 0 in order to release
a stack frame.
---
gcc/asan.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/gcc/asan.c b/gcc/asan.c
index c9872f1b007..232341f5c4b 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1598,8 +1598,24 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
if (use_after_return_class < 5
&& can_store_by_pieces (sz, builtin_memset_read_str, &c,
BITS_PER_UNIT, true))
- store_by_pieces (shadow_mem, sz, builtin_memset_read_str, &c,
- BITS_PER_UNIT, true, RETURN_BEGIN);
+ {
+ /* Emit:
+ memset(ShadowBase, kAsanStackAfterReturnMagic, ShadowSize);
+ **SavedFlagPtr(FakeStack) = 0
+ */
+ store_by_pieces (shadow_mem, sz, builtin_memset_read_str, &c,
+ BITS_PER_UNIT, true, RETURN_BEGIN);
+
+ unsigned HOST_WIDE_INT offset
+ = (1 << (use_after_return_class + 6));
+ offset -= GET_MODE_SIZE (ptr_mode);
+ mem = adjust_address (mem, ptr_mode, offset);
+ rtx addr = gen_reg_rtx (ptr_mode);
+ emit_move_insn (addr, mem);
+ mem = gen_rtx_MEM (ptr_mode, addr);
+ mem = adjust_address (mem, QImode, 0);
+ emit_move_insn (mem, const0_rtx);
+ }
else if (use_after_return_class >= 5
|| !set_storage_via_setmem (shadow_mem,
GEN_INT (sz),
--
2.26.2
