On Tue, 2020-07-07 at 16:19 -0700, Carl Love wrote:
> Segher:
>
> I have fixed the issues you mentioned in version 2. I also rebased the
> patch onto the latest mainline. This resulted in having to change
> FUTURE to P10 everywhere.
>
> I reran regression testing on Power 9 with no regression issues.
> I also ran test cases manually on mambo.
>
> Please let me know if the patch is acceptable for mainline. Thanks for
> your time and previous reviews of the patch.
>
> Carl Love
> -----------------------------------------------------
>
> version 3 Changes
> rebased onto mainline 7/7/2020
> Change FUTURE to P10 in code and ChangeLog.
> ChangeLog, fixed the name of a couple of files which were wrong.
> Reformated define_mode_attr VSX_MM_SUFFIX definition to shorten the
> line.
> Reworked define_expand "vec_mtvsrbm_mtvsrbmi" as it will not work as
> intended.
And renamed? I don't see vec_mtvsrbm_mtvsrbmi referenced in the patch.
Did this get renamed back to vec_mtvsrbm, reversing that version 2 change?
> Changed vsx_register_operand to altivec_register_operand for "v"
> constraint.
> Removed --save-temps from test cases as it is not needed.
>
>
> -----------------------------------------------
> version 2 Changes
>
> Addressed Will's comments
> - ChangeLog: fixed name/symbol order;
> changed reference from rs6000-c.c to rs6000-builtin.def.
>
> - define_expand "vec_mtvsrbm": changed name to vec_mtvsrbm_mtvsrbmi,
> updated comment
>
> - vsx_mask-runnable.c: divided it up into four smaller test cases,
> vsx_mask-count-runnable.c, vsx_mask-expane-runnable.c,
> vsx_mask-extract-runnable.c, vsx_mask-move-runnable.c.
>
> -------------------------------------------------------
> RS6000 RFC 2629, add VSX mask manipulation support
>
> The following patch adds support for builtins vec_genbm(), vec_genhm(),
> vec_genwm(), vec_gendm(), vec_genqm(), vec_cntm(), vec_expandm(),
> vec_extractm(). Support for instructions mtvsrbm, mtvsrhm, mtvsrwm,
> mtvsrdm, mtvsrqm, cntm, vexpandm, vextractm.
>
> The test has been tested on:
>
> powerpc64le-unknown-linux-gnu (Power 9 LE)
>
> and mambo with no regression errors.
>
> Please let me know if this patch is acceptable for inclusion in the mainline
> branch. Thanks.
>
> Carl Love
> -------------------------------------------------------------------
>
> RS6000, add VSX mask manipulation support
>
> gcc/ChangeLog
>
> 2020-07-07 Carl Love <c...@us.ibm.com>
>
> * config/rs6000/vsx.md (VSX_MM): New define_mode_iterator.
> (VSX_MM4): New define_mode_iterator.
> (VSX_MM_SUFFIX4): New define_mode_attr.
> (vec_mtvsrbm): New define_expand.
This (vec_mtvsrbm) is commented out in the patch below.
> (vec_mtvsrbmi): New define_insn.
> (vec_mtvsr_<mode>): New define_insn.
> (vec_cntmb_<mode>): New define_insn.
> (vec_extract_<mode>): New define_insn.
> (vec_expand_<mode>): New define_insn.
> (define_c_enum unspec): Add entries UNSPEC_MTVSBM, UNSPEC_VCNTMB,
> UNSPEC_VEXTRACT, UNSPEC_VEXPAND.
> * config/rs6000/altivec.h ( vec_genbm, vec_genhm, vec_genwm,
> vec_gendm, vec_genqm, vec_cntm, vec_expandm, vec_extractm): Add
> defines.
> * config/rs6000/rs6000-builtin.def: Add defines BU_P10_2, BU_P10_1.
> (BU_P10_1): Add definitions for mtvsrbm, mtvsrhm, mtvsrwm,
> mtvsrdm, mtvsrqm, vexpandmb, vexpandmh, vexpandmw, vexpandmd,
> vexpandmq, vextractmb, vextractmh, vextractmw, vextractmd, vextractmq.
> (BU_P10_2): Add definitions for cntmbb, cntmbh, cntmbw, cntmbd.
> (BU_P10_OVERLOAD_1): Add definitions for mtvsrbm, mtvsrhm,
> mtvsrwm, mtvsrdm, mtvsrqm, vexpandm, vextractm.
> (BU_P10_OVERLOAD_2): Add defition for cntm.
> * config/rs6000/rs6000-call.c (rs6000_expand_binop_builtin): Add
> checks for CODE_FOR_vec_cntmbb_v16qi, CODE_FOR_vec_cntmb_v8hi,
> CODE_FOR_vec_cntmb_v4si, CODE_FOR_vec_cntmb_v2di.
> (altivec_overloaded_builtins): Add overloaded argument entries for
> FUTURE_BUILTIN_VEC_MTVSRBM, FUTURE_BUILTIN_VEC_MTVSRHM,
> FUTURE_BUILTIN_VEC_MTVSRWM, FUTURE_BUILTIN_VEC_MTVSRDM,
> FUTURE_BUILTIN_VEC_MTVSRQM, FUTURE_BUILTIN_VEC_VCNTMBB,
> FUTURE_BUILTIN_VCNTMBB, FUTURE_BUILTIN_VCNTMBH,
> FUTURE_BUILTIN_VCNTMBW, FUTURE_BUILTIN_VCNTMBD,
> FUTURE_BUILTIN_VEXPANDMB, FUTURE_BUILTIN_VEXPANDMH,
> FUTURE_BUILTIN_VEXPANDMW, FUTURE_BUILTIN_VEXPANDMD,
> FUTURE_BUILTIN_VEXPANDMQ, FUTURE_BUILTIN_VEXTRACTMB,
> FUTURE_BUILTIN_VEXTRACTMH, FUTURE_BUILTIN_VEXTRACTMW,
> FUTURE_BUILTIN_VEXTRACTMD, FUTURE_BUILTIN_VEXTRACTMQ.
> (builtin_function_type): Add case entries for FUTURE_BUILTIN_MTVSRBM,
> FUTURE_BUILTIN_MTVSRHM, FUTURE_BUILTIN_MTVSRWM, FUTURE_BUILTIN_MTVSRDM,
> FUTURE_BUILTIN_MTVSRQM, FUTURE_BUILTIN_VCNTMBB, FUTURE_BUILTIN_VCNTMBH,
> FUTURE_BUILTIN_VCNTMBW, FUTURE_BUILTIN_VCNTMBD,
> FUTURE_BUILTIN_VEXPANDMB, FUTURE_BUILTIN_VEXPANDMH,
> FUTURE_BUILTIN_VEXPANDMW, FUTURE_BUILTIN_VEXPANDMD,
> FUTURE_BUILTIN_VEXPANDMQ.
These should be updated to reflect the FUTURE -> P10 naming change.
> * config/rs6000/rs6000-builtin.def (altivec_overloaded_builtins): Add
> entries for MTVSRBM, MTVSRHM, MTVSRWM, MTVSRDM, MTVSRQM, VCNTM,
> VEXPANDM, VEXTRACTM.
>
> gcc/testsuite/ChangeLog
>
> 2020-07-07 Carl Love <c...@us.ibm.com>
> * gcc.target/powerpc/vsx_mask-count-runnable.c: New test case.
> * gcc.target/powerpc/vsx_mask-expand-runnable.c: New test case.
> * gcc.target/powerpc/vsx_mask-extract-runnable.c: New test case.
> * gcc.target/powerpc/vsx_mask-move-runnable.c: New test case.
> ---
> gcc/config/rs6000/altivec.h | 10 +
> gcc/config/rs6000/rs6000-builtin.def | 45 ++++
> gcc/config/rs6000/rs6000-call.c | 66 ++++-
> gcc/config/rs6000/vsx.md | 67 ++++++
> .../powerpc/vsx_mask-count-runnable.c | 149 ++++++++++++
> .../powerpc/vsx_mask-expand-runnable.c | 194 +++++++++++++++
> .../powerpc/vsx_mask-extract-runnable.c | 162 +++++++++++++
> .../powerpc/vsx_mask-move-runnable.c | 225 ++++++++++++++++++
> 8 files changed, 917 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
> create mode 100644
> gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
> create mode 100644
> gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
>
> diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
> index bb1524f4a67..43e28d957a9 100644
> --- a/gcc/config/rs6000/altivec.h
> +++ b/gcc/config/rs6000/altivec.h
> @@ -710,6 +710,16 @@ __altivec_scalar_pred(vec_any_nle,
>
> #define vec_strir_p(a) __builtin_vec_strir_p (a)
> #define vec_stril_p(a) __builtin_vec_stril_p (a)
> +
> +/* VSX Mask Manipulation builtin. */
> +#define vec_genbm __builtin_vec_mtvsrbm
> +#define vec_genhm __builtin_vec_mtvsrhm
> +#define vec_genwm __builtin_vec_mtvsrwm
> +#define vec_gendm __builtin_vec_mtvsrdm
> +#define vec_genqm __builtin_vec_mtvsrqm
> +#define vec_cntm __builtin_vec_cntm
> +#define vec_expandm __builtin_vec_vexpandm
> +#define vec_extractm __builtin_vec_vextractm
> #endif
>
> #endif /* _ALTIVEC_H */
> diff --git a/gcc/config/rs6000/rs6000-builtin.def
> b/gcc/config/rs6000/rs6000-builtin.def
> index 363656ec05c..138976bf4ff 100644
> --- a/gcc/config/rs6000/rs6000-builtin.def
> +++ b/gcc/config/rs6000/rs6000-builtin.def
> @@ -1128,6 +1128,22 @@
> (RS6000_BTC_ ## ATTR /* ATTR */ \
> | RS6000_BTC_TERNARY), \
> CODE_FOR_ ## ICODE) /* ICODE */
> +
> +#define BU_P10_1(ENUM, NAME, ATTR, ICODE) \
> + RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
> + "__builtin_vec" NAME, /* NAME */ \
> + RS6000_BTM_P10, /* MASK */ \
> + (RS6000_BTC_ ## ATTR /* ATTR */ \
> + | RS6000_BTC_UNARY), \
> + CODE_FOR_ ## ICODE) /* ICODE */
> +
> +#define BU_P10_2(ENUM, NAME, ATTR, ICODE) \
> + RS6000_BUILTIN_2 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
> + "__builtin_vec" NAME, /* NAME */ \
> + RS6000_BTM_P10, /* MASK */ \
> + (RS6000_BTC_ ## ATTR /* ATTR */ \
> + | RS6000_BTC_BINARY), \
> + CODE_FOR_ ## ICODE) /* ICODE */
> #endif
>
>
> @@ -2718,6 +2734,26 @@ BU_P10V_1 (VSTRIHR_P, "vstrihr_p", CONST,
> vstrir_p_v8hi)
> BU_P10V_1 (VSTRIBL_P, "vstribl_p", CONST, vstril_p_v16qi)
> BU_P10V_1 (VSTRIHL_P, "vstrihl_p", CONST, vstril_p_v8hi)
>
> +BU_P10V_1 (MTVSRBM, "mtvsrbm", CONST, vec_mtvsr_v16qi)
> +BU_P10V_1 (MTVSRHM, "mtvsrhm", CONST, vec_mtvsr_v8hi)
> +BU_P10V_1 (MTVSRWM, "mtvsrwm", CONST, vec_mtvsr_v4si)
> +BU_P10V_1 (MTVSRDM, "mtvsrdm", CONST, vec_mtvsr_v2di)
> +BU_P10V_1 (MTVSRQM, "mtvsrqm", CONST, vec_mtvsr_v1ti)
> +BU_P10V_2 (VCNTMBB, "cntmbb", CONST, vec_cntmb_v16qi)
> +BU_P10V_2 (VCNTMBH, "cntmbh", CONST, vec_cntmb_v8hi)
> +BU_P10V_2 (VCNTMBW, "cntmbw", CONST, vec_cntmb_v4si)
> +BU_P10V_2 (VCNTMBD, "cntmbd", CONST, vec_cntmb_v2di)
> +BU_P10V_1 (VEXPANDMB, "vexpandmb", CONST, vec_expand_v16qi)
> +BU_P10V_1 (VEXPANDMH, "vexpandmh", CONST, vec_expand_v8hi)
> +BU_P10V_1 (VEXPANDMW, "vexpandmw", CONST, vec_expand_v4si)
> +BU_P10V_1 (VEXPANDMD, "vexpandmd", CONST, vec_expand_v2di)
> +BU_P10V_1 (VEXPANDMQ, "vexpandmq", CONST, vec_expand_v1ti)
> +BU_P10V_1 (VEXTRACTMB, "vextractmb", CONST, vec_extract_v16qi)
> +BU_P10V_1 (VEXTRACTMH, "vextractmh", CONST, vec_extract_v8hi)
> +BU_P10V_1 (VEXTRACTMW, "vextractmw", CONST, vec_extract_v4si)
> +BU_P10V_1 (VEXTRACTMD, "vextractmd", CONST, vec_extract_v2di)
> +BU_P10V_1 (VEXTRACTMQ, "vextractmq", CONST, vec_extract_v1ti)
> +
> /* Overloaded vector builtins for ISA 3.1 (power10). */
> BU_P10_OVERLOAD_2 (CLRL, "clrl")
> BU_P10_OVERLOAD_2 (CLRR, "clrr")
> @@ -2734,6 +2770,15 @@ BU_P10_OVERLOAD_1 (VSTRIL, "stril")
> BU_P10_OVERLOAD_1 (VSTRIR_P, "strir_p")
> BU_P10_OVERLOAD_1 (VSTRIL_P, "stril_p")
>
> +BU_P10_OVERLOAD_1 (MTVSRBM, "mtvsrbm")
> +BU_P10_OVERLOAD_1 (MTVSRHM, "mtvsrhm")
> +BU_P10_OVERLOAD_1 (MTVSRWM, "mtvsrwm")
> +BU_P10_OVERLOAD_1 (MTVSRDM, "mtvsrdm")
> +BU_P10_OVERLOAD_1 (MTVSRQM, "mtvsrqm")
> +BU_P10_OVERLOAD_2 (VCNTM, "cntm")
> +BU_P10_OVERLOAD_1 (VEXPANDM, "vexpandm")
> +BU_P10_OVERLOAD_1 (VEXTRACTM, "vextractm")
> +
> /* 1 argument crypto functions. */
> BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox_v2di)
> BU_CRYPTO_1 (VSBOX_BE, "vsbox_be", CONST,
> crypto_vsbox_v16qi)
> diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
> index d3cf2de8878..b7aae7670af 100644
> --- a/gcc/config/rs6000/rs6000-call.c
> +++ b/gcc/config/rs6000/rs6000-call.c
> @@ -5629,6 +5629,52 @@ const struct altivec_builtin_types
> altivec_overloaded_builtins[] = {
> { P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIHR_P,
> RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
>
> + { P10_BUILTIN_VEC_MTVSRBM, P10_BUILTIN_MTVSRBM,
> + RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI, 0, 0 },
> + { P10_BUILTIN_VEC_MTVSRHM, P10_BUILTIN_MTVSRHM,
> + RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTDI, 0, 0 },
> + { P10_BUILTIN_VEC_MTVSRWM, P10_BUILTIN_MTVSRWM,
> + RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTDI, 0, 0 },
> + { P10_BUILTIN_VEC_MTVSRDM, P10_BUILTIN_MTVSRDM,
> + RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI, 0, 0 },
> + { P10_BUILTIN_VEC_MTVSRQM, P10_BUILTIN_MTVSRQM,
> + RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTDI, 0, 0 },
> +
> + { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBB,
> + RS6000_BTI_unsigned_long_long,
> + RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI, 0 },
> + { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBH,
> + RS6000_BTI_unsigned_long_long,
> + RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI, 0 },
> + { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBW,
> + RS6000_BTI_unsigned_long_long,
> + RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI, 0 },
> + { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBD,
> + RS6000_BTI_unsigned_long_long,
> + RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI, 0 },
> +
> + { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMB,
> + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
> + { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMH,
> + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
> + { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMW,
> + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
> + { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMD,
> + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
> + { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMQ,
> + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
> +
> + { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMB,
> + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
> + { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMH,
> + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
> + { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMW,
> + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 0, 0 },
> + { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMD,
> + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 0, 0 },
> + { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMQ,
> + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, 0, 0 },
> +
> { RS6000_BUILTIN_NONE, RS6000_BUILTIN_NONE, 0, 0, 0, 0 }
> };
>
> @@ -9034,7 +9080,11 @@ rs6000_expand_binop_builtin (enum insn_code icode,
> tree exp, rtx target)
> || icode == CODE_FOR_unpackkf
> || icode == CODE_FOR_unpacktf
> || icode == CODE_FOR_unpackif
> - || icode == CODE_FOR_unpacktd)
> + || icode == CODE_FOR_unpacktd
> + || icode == CODE_FOR_vec_cntmb_v16qi
> + || icode == CODE_FOR_vec_cntmb_v8hi
> + || icode == CODE_FOR_vec_cntmb_v4si
> + || icode == CODE_FOR_vec_cntmb_v2di)
> {
> /* Only allow 1-bit unsigned literals. */
> STRIP_NOPS (arg1);
> @@ -13669,6 +13719,20 @@ builtin_function_type (machine_mode mode_ret,
> machine_mode mode_arg0,
> case MISC_BUILTIN_CBCDTD:
> case VSX_BUILTIN_XVCVSPBF16:
> case VSX_BUILTIN_XVCVBF16SP:
> + case P10_BUILTIN_MTVSRBM:
> + case P10_BUILTIN_MTVSRHM:
> + case P10_BUILTIN_MTVSRWM:
> + case P10_BUILTIN_MTVSRDM:
> + case P10_BUILTIN_MTVSRQM:
> + case P10_BUILTIN_VCNTMBB:
> + case P10_BUILTIN_VCNTMBH:
> + case P10_BUILTIN_VCNTMBW:
> + case P10_BUILTIN_VCNTMBD:
> + case P10_BUILTIN_VEXPANDMB:
> + case P10_BUILTIN_VEXPANDMH:
> + case P10_BUILTIN_VEXPANDMW:
> + case P10_BUILTIN_VEXPANDMD:
> + case P10_BUILTIN_VEXPANDMQ:
> h.uns_p[0] = 1;
> h.uns_p[1] = 1;
> break;
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 732a54842b6..a74db0f6f5e 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -263,6 +263,17 @@
> ;; Mode attribute to give the suffix for the splat instruction
> (define_mode_attr VSX_SPLAT_SUFFIX [(V16QI "b") (V8HI "h")])
>
> +;; Iterator for the move to mask instructions
> +(define_mode_iterator VSX_MM [V16QI V8HI V4SI V2DI V1TI])
> +(define_mode_iterator VSX_MM4 [V16QI V8HI V4SI V2DI])
> +
> +;; Mode attribute to give the suffix for the mask instruction
> +(define_mode_attr VSX_MM_SUFFIX [(V16QI "b")
> + (V8HI "h")
> + (V4SI "w")
> + (V2DI "d")
> + (V1TI "q")])
> +
> ;; Constants for creating unspecs
> (define_c_enum "unspec"
> [UNSPEC_VSX_CONCAT
> @@ -347,6 +358,10 @@
> UNSPEC_VSX_FIRST_MISMATCH_INDEX
> UNSPEC_VSX_FIRST_MISMATCH_EOS_INDEX
> UNSPEC_XXGENPCV
> + UNSPEC_MTVSBM
> + UNSPEC_VCNTMB
> + UNSPEC_VEXPAND
> + UNSPEC_VEXTRACT
> ])
>
> (define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16
> @@ -5701,3 +5716,55 @@
> "TARGET_POWER10"
> "<xvcvbf16> %x0,%x1"
> [(set_attr "type" "vecfloat")])
> +
> +;; VSX mask manipulation instructions
> +;;;(define_expand "vec_mtvsrbm"
> +;;; [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
> +;;; (unspec:V16QI [(match_operand:DI 1 "gpc_reg_operand" "b")]
> +;;; UNSPEC_MTVSBM))]
> +;;; "TARGET_POWER10"
> +;;; {
> +;;; emit_insn (gen_vec_mtvsr_v16qi (operands[0], operands[1]));
> +;;; DONE;
> +;;;})
If it's not necessary, drop it. Not clear to me why, so also include
something in the version X changes blurb to describe this change.
> +
> +(define_insn "vec_mtvsrbmi"
> + [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
> + (unspec:V16QI [(match_operand:QI 1 "u6bit_cint_operand" "n")]
> + UNSPEC_MTVSBM))]
> + "TARGET_POWER10"
> + "mtvsrbmi %0,%1"
> +)
> +
> +(define_insn "vec_mtvsr_<mode>"
> + [(set (match_operand:VSX_MM 0 "altivec_register_operand" "=v")
> + (unspec:VSX_MM [(match_operand:DI 1 "gpc_reg_operand" "b")]
> + UNSPEC_MTVSBM))]
> + "TARGET_POWER10"
> + "mtvsr<VSX_MM_SUFFIX>m %0,%1";
> + [(set_attr "type" "vecsimple")])
> +
> +(define_insn "vec_cntmb_<mode>"
> + [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
> + (unspec:DI [(match_operand:VSX_MM4 1 "altivec_register_operand" "v")
> + (match_operand:QI 2 "const_0_to_1_operand" "n")]
> + UNSPEC_VCNTMB))]
> + "TARGET_POWER10"
> + "vcntmb<VSX_MM_SUFFIX> %0,%1,%2"
> + [(set_attr "type" "vecsimple")])
> +
> +(define_insn "vec_extract_<mode>"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec:SI [(match_operand:VSX_MM 1 "altivec_register_operand" "v")]
> + UNSPEC_VEXTRACT))]
> + "TARGET_POWER10"
> + "vextract<VSX_MM_SUFFIX>m %0,%1"
> + [(set_attr "type" "vecsimple")])
> +
> +(define_insn "vec_expand_<mode>"
> + [(set (match_operand:VSX_MM 0 "vsx_register_operand" "=v")
> + (unspec:VSX_MM [(match_operand:VSX_MM 1 "vsx_register_operand" "v")]
> + UNSPEC_VEXPAND))]
> + "TARGET_POWER10"
> + "vexpand<VSX_MM_SUFFIX>m %0,%1"
> + [(set_attr "type" "vecsimple")])
<snip>
Thanks,
-Will
