On Fri, 2020-09-25 at 12:36 -0500, Segher Boessenkool wrote: > Hi! > > On Thu, Sep 24, 2020 at 03:35:24PM -0500, will schmidt wrote: > > We have extraneous BTM entry (RS6000_BTM_POWERPC64) in the > > define for > > our P10 MISC 2 builtin definition. This does not exist for the > > '0', > > '1' or '3' definitions. It appears to me that this was erroneously > > copied from the P7 version of the define which contains a version > > of the > > BU macro both with and without that element. Removing the > > RS6000_BTM_POWERPC64 portion of the define does not introduce any > > obvious > > failures, I believe this extra line can be safely removed. > > No, it cannot. > > This is used for pdepd/pextd/cntlzdm/cnttzdm/cfuged, all of which do > need 64-bit registers to do anything sane. > > This should really have defined some new builtin class, and I thought > we > could just be tricky and take a massive shortcut. Bill has been hit > by > this already as well, sigh :-(
Ok. The usage of that macro seems to be limited to those that you have referenced. i.e. /* Builtins for scalar instructions added in ISA 3.1 (power10). */ BU_P10_MISC_2 (CFUGED, "cfuged", CONST, cfuged) BU_P10_MISC_2 (CNTLZDM, "cntlzdm", CONST, cntlzdm) BU_P10_MISC_2 (CNTTZDM, "cnttzdm", CONST, cnttzdm) BU_P10_MISC_2 (PDEPD, "pdepd", CONST, pdepd) BU_P10_MISC_2 (PEXTD, "pextd", CONST, pextd) So looking at the power7 entries that have the BTM_POWERPC64 entry.. BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si) BU_P7_MISC_2 (DIVWEU, "divweu", CONST, diveu_si) BU_P7_POWERPC64_MISC_2 (DIVDE, "divde", CONST, dive_di) BU_P7_POWERPC64_MISC_2 (DIVDEU, "divdeu", CONST, diveu_di) Would it be suitable to rename the P10 macro to BU_P10_POWERPC64_MISC_2 ? I'd then debate whether to add a unused macro to fill the gap between BU_P10_MISC_1 and BU_P10_MISC_2 If you've got schemes for a deeper fix, i'd need another hint. :-) thanks -Will > > > Segher
