This patch backports the AArch32 support for Arm's Neoverse N2 CPU to GCC 8.
Testing: * Bootstrapped and regtested on arm-none-linux-gnueabihf. OK for GCC 8 branch? Thanks, Alex --- gcc/ChangeLog: * config/arm/arm-cpus.in (neoverse-n2): New. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. * config/arm/driver-arm.c (arm_cpu_table): Add Neoverse N2. * doc/invoke.texi: Document support for Neoverse N2.
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index edfe5b378da..39a9e8b76ba 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1588,6 +1588,17 @@ begin cpu neoverse-v1 end cpu neoverse-v1 +# Armv8.5 A-profile Architecture Processors +begin cpu neoverse-n2 + cname neoversen2 + tune for cortex-a57 + tune flags LDSCHED + architecture armv8.4-a+fp16 + option crypto add FP_ARMv8 CRYPTO + costs cortex_a57 +end cpu neoverse-n2 + + # V8 M-profile implementations. begin cpu cortex-m23 cname cortexm23 diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 36dba62003a..a0fb8323ee3 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -354,6 +354,9 @@ Enum(processor_type) String(cortex-a75.cortex-a55) Value( TARGET_CPU_cortexa75co EnumValue Enum(processor_type) String(neoverse-v1) Value( TARGET_CPU_neoversev1) +EnumValue +Enum(processor_type) String(neoverse-n2) Value( TARGET_CPU_neoversen2) + EnumValue Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index c972ce55576..ea3dbcda43f 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -57,6 +57,6 @@ cortexa73,exynosm1,xgene1, cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35, cortexa73cortexa53,cortexa55,cortexa75, - cortexa75cortexa55,neoversev1,cortexm23, - cortexm33,cortexr52" + cortexa75cortexa55,neoversev1,neoversen2, + cortexm23,cortexm33,cortexr52" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c index a53c2272864..45ad92ef0e0 100644 --- a/gcc/config/arm/driver-arm.c +++ b/gcc/config/arm/driver-arm.c @@ -56,6 +56,7 @@ static struct vendor_cpu arm_cpu_table[] = { {"0xd09", "armv8-a+crc", "cortex-a73"}, {"0xd05", "armv8.2-a+fp16+dotprod", "cortex-a55"}, {"0xd0a", "armv8.2-a+fp16+dotprod", "cortex-a75"}, + {"0xd49", "armv8.4-a+fp16", "neoverse-n2"}, {"0xc14", "armv7-r", "cortex-r4"}, {"0xc15", "armv7-r", "cortex-r5"}, {"0xc17", "armv7-r", "cortex-r7"}, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b91366daafd..78ca7738df2 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -16334,8 +16334,8 @@ Permissible names are: @samp{arm2}, @samp{arm250}, @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17}, @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, -@samp{neoverse-v1}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, -@samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, +@samp{neoverse-v1}, @samp{neoverse-n2}, @samp{cortex-r4}, @samp{cortex-r4f}, +@samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, @samp{cortex-m33}, @samp{cortex-m23}, @samp{cortex-m7},