On Wed, 2020-11-04 at 14:42 -0600, Pat Haugen via Gcc-patches wrote: > Update instruction attributes for Power10. > > > This patch updates the type/prefixed/dot/size attributes for various new > instructions (and a couple existing that were incorrect) in preparation for > the Power10 scheduling patch that will be following. > > Bootstrap/regtest on powerpc64le (Power8/Power10) with no new regressions. Ok > for trunk? > > -Pat > > > 2020-11-04 Pat Haugen <pthau...@linux.ibm.com> > > gcc/ > * config/rs6000/altivec.md (vs<SLDB_lr>db_<mode>, xxspltiw_v4si, > xxspltiw_v4sf_inst, xxspltidp_v2df_inst, xxsplti32dx_v4si_inst, > xxsplti32dx_v4sf_inst, xxblend_<mode>, xxpermx_inst, > vstrir_code_<mode>, vstrir_p_code_<mode>, vstril_code_<mode>, > vstril_p_code_<mode>, altivec_lvsl_reg, altivec_lvsl_direct, > altivec_lvsr_reg, altivec_lvsr_direct, xxeval, vcfuged, vclzdm, > vctzdm, vpdepd, vpextd, vgnb, vclrlb, vclrrb): Update instruction > attributes for Power10. > * config/rs6000/dfp.md (extendddtd2, trunctddd2, *cmp<mode>_internal1, > floatditd2, ftrunc<mode>2, fix<mode>di2, dfp_ddedpd_<mode>, > dfp_denbcd_<mode>, dfp_dxex_<mode>, dfp_diex_<mode>, > *dfp_sgnfcnc_<mode>, dfp_dscli_<mode>, dfp_dscri_<mode>): Likewise. > * config/rs6000/mma.md (*movpoi, mma_<vvi4i4i8>, mma_<avvi4i4i8>, > mma_<vvi4i4i2>, mma_<avvi4i4i2>, mma_<vvi4i4>, mma_<avvi4i4>, > mma_<pvi4i2>, mma_<apvi4i2>, mma_<vvi4i4i4>, mma_<avvi4i4i4>): > Likewise. > * config/rs6000/rs6000.c (rs6000_final_prescan_insn): Only add 'p' for > PREFIXED_YES.
The code change reads as roughly - next_insns_prefixed_p != PREFIXED_NO + next_insn_prefixed_p == PREFIXED_YES" So just an inversion of the logic? I don't obviously see the 'p' impact there. > * config/rs6000/rs6000.md (define_attr "size"): Add 256. > (define_attr "prefixed"): Add 'always'. > (define_mode_attr bits): Add DD/TD modes. > (cfuged, cntlzdm, cnttzdm, pdepd, pextd, bswaphi2_reg, bswapsi2_reg, > bswapdi2_brd, setbc_<un>signed_<GPR:mode>, > *setbcr_<un>signed_<GPR:mode>, *setnbc_<un>signed_<GPR:mode>, > *setnbcr_<un>signed_<GPR:mode>): Update instruction attributes for > Power10. ok. (assuming the assorted 'integer' -> 'crypto' changes are correct, of course). > * config/rs6000/sync.md (load_quadpti, store_quadpti, load_lockedpti, > store_conditionalpti): Update instruction attributes for Power10. > * config/rs6000/vsx.md (*xvtlsbb_internal, xxgenpcvm_<mode>_internal, > vextractl<mode>_internal, vextractr<mode>_internal, > vinsertvl_internal_<mode>, vinsertvr_internal_<mode>, > vinsertgl_internal_<mode>, vinsertgr_internal_<mode>, > vreplace_elt_<mode>_inst): Likewise. lgtm, thanks -Will >
