Hi:
This patch reduce reservation of model do not more than 10 cycles. The
memory of genautomata down to 1GB.
ChangeLog
gcc/
PR target/77510
* config/mips/gs464.md: Reduce reservation
duration to 10 cycles.
* config/mips/i6400.md: Likewise.
* config/mips/m5100.md: Likewise.
* config/mips/p5600.md: Likewise.
* config/mips/p6600.md: Likewise.
* config/mips/xlp.md: Likewise.
* config/mips/xlr.md: Likewise.
>From 29fa1d943a30d97fb888980b1dcfdf38b12b67d9 Mon Sep 17 00:00:00 2001
From: Chenghua Xu <xucheng...@loongson.cn>
Date: Tue, 10 Nov 2020 19:04:48 +0800
Subject: [PATCH] [MIPS] Reduce size of MIPS core automaton.
gcc/
PR target/77510
* config/mips/gs464.md: Reduce reservation
duration to 10 cycles.
* config/mips/i6400.md: Likewise.
* config/mips/m5100.md: Likewise.
* config/mips/p5600.md: Likewise.
* config/mips/p6600.md: Likewise.
* config/mips/xlp.md: Likewise.
* config/mips/xlr.md: Likewise.
---
gcc/config/mips/gs464.md | 8 ++++----
gcc/config/mips/i6400.md | 16 ++++++++--------
gcc/config/mips/m5100.md | 10 +++++-----
gcc/config/mips/p5600.md | 2 +-
gcc/config/mips/p6600.md | 2 +-
gcc/config/mips/xlp.md | 20 ++++++++++----------
gcc/config/mips/xlr.md | 4 ++--
7 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/gcc/config/mips/gs464.md b/gcc/config/mips/gs464.md
index c936c74c8c0..3cd51a5c3bf 100644
--- a/gcc/config/mips/gs464.md
+++ b/gcc/config/mips/gs464.md
@@ -71,13 +71,13 @@
(and (eq_attr "cpu" "gs464")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "SI")))
- "gs464_alu2 * 12")
+ "gs464_alu2 * 10")
(define_insn_reservation "gs464_idiv_di" 25
(and (eq_attr "cpu" "gs464")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "DI")))
- "gs464_alu2 * 25")
+ "gs464_alu2 * 10")
(define_insn_reservation "gs464_load" 3
(and (eq_attr "cpu" "gs464")
@@ -120,13 +120,13 @@
(and (eq_attr "cpu" "gs464")
(and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
(eq_attr "mode" "SF")))
- "gs464_falu1 * 12")
+ "gs464_falu1 * 10")
(define_insn_reservation "gs464_fdiv_df" 19
(and (eq_attr "cpu" "gs464")
(and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
(eq_attr "mode" "DF")))
- "gs464_falu1 * 19")
+ "gs464_falu1 * 10")
;; Force single-dispatch for unknown or multi.
(define_insn_reservation "gs464_unknown" 1
diff --git a/gcc/config/mips/i6400.md b/gcc/config/mips/i6400.md
index 5db9f7098c1..5a3c907110e 100644
--- a/gcc/config/mips/i6400.md
+++ b/gcc/config/mips/i6400.md
@@ -99,21 +99,21 @@
(and (eq_attr "cpu" "i6400")
(and (eq_attr "mode" "V2DI")
(eq_attr "type" "simd_div")))
- "i6400_fpu_short+i6400_fpu_div*36")
+ "i6400_fpu_short+i6400_fpu_div*10")
;; div.w, mod.w (non-pipelined)
(define_insn_reservation "i6400_msa_div_w" 20
(and (eq_attr "cpu" "i6400")
(and (eq_attr "mode" "V4SI")
(eq_attr "type" "simd_div")))
- "i6400_fpu_short+i6400_fpu_div*20")
+ "i6400_fpu_short+i6400_fpu_div*10")
;; div.h, mod.h (non-pipelined)
(define_insn_reservation "i6400_msa_div_h" 12
(and (eq_attr "cpu" "i6400")
(and (eq_attr "mode" "V8HI")
(eq_attr "type" "simd_div")))
- "i6400_fpu_short+i6400_fpu_div*12")
+ "i6400_fpu_short+i6400_fpu_div*10")
;; div.b, mod.b (non-pipelined)
(define_insn_reservation "i6400_msa_div_b" 8
@@ -201,13 +201,13 @@
(and (eq_attr "cpu" "i6400")
(and (eq_attr "mode" "V2DF")
(eq_attr "type" "simd_fdiv")))
- "i6400_fpu_long+i6400_fpu_float_l*30")
+ "i6400_fpu_long+i6400_fpu_float_l*10")
;; fdiv.w
(define_insn_reservation "i6400_msa_fdiv_sf" 22
(and (eq_attr "cpu" "i6400")
(eq_attr "type" "simd_fdiv"))
- "i6400_fpu_long+i6400_fpu_float_l*22")
+ "i6400_fpu_long+i6400_fpu_float_l*10")
;;
;; FPU pipe
@@ -236,13 +236,13 @@
(and (eq_attr "cpu" "i6400")
(and (eq_attr "mode" "DF")
(eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")))
- "i6400_fpu_long+i6400_fpu_apu*30")
+ "i6400_fpu_long+i6400_fpu_apu*10")
;; div, sqrt (Single Precision)
(define_insn_reservation "i6400_fpu_div_sf" 22
(and (eq_attr "cpu" "i6400")
(eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt"))
- "i6400_fpu_long+i6400_fpu_apu*22")
+ "i6400_fpu_long+i6400_fpu_apu*10")
;; sdc1, swc1
(define_insn_reservation "i6400_fpu_store" 1
@@ -312,7 +312,7 @@
(define_insn_reservation "i6400_int_div" 32
(and (eq_attr "cpu" "i6400")
(eq_attr "type" "idiv,idiv3"))
- "i6400_gpdiv*32")
+ "i6400_gpdiv*10")
;; Load lb, lbu, lh, lhu, lq, lw, lw_i2f, lwxs
(define_insn_reservation "i6400_int_load" 3
diff --git a/gcc/config/mips/m5100.md b/gcc/config/mips/m5100.md
index 3e1c2e7303f..58534fac817 100644
--- a/gcc/config/mips/m5100.md
+++ b/gcc/config/mips/m5100.md
@@ -109,7 +109,7 @@
(define_insn_reservation "m51_int_div_si" 34
(and (eq_attr "cpu" "m5100")
(eq_attr "type" "idiv"))
- "m51_alu+m51_mul*34")
+ "m51_alu+m51_mul*10")
;; --------------------------------------------------------------
;; Floating Point Instructions
@@ -164,26 +164,26 @@
(and (eq_attr "cpu" "m5100")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "SF")))
- "m51_fpu*14")
+ "m51_fpu*10")
(define_insn_reservation "m51_fdiv_df" 32
(and (eq_attr "cpu" "m5100")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "DF")))
- "m51_fpu*29")
+ "m51_fpu*10")
;; frsqrt
(define_insn_reservation "m51_frsqrt_sf" 17
(and (eq_attr "cpu" "m5100")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "SF")))
- "m51_fpu*14")
+ "m51_fpu*10")
(define_insn_reservation "m51_frsqrt_df" 35
(and (eq_attr "cpu" "m5100")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "DF")))
- "m51_fpu*31")
+ "m51_fpu*10")
;; fcmp
(define_insn_reservation "m51_fcmp" 4
diff --git a/gcc/config/mips/p5600.md b/gcc/config/mips/p5600.md
index 29c2d2b64c1..6b2df399bb9 100644
--- a/gcc/config/mips/p5600.md
+++ b/gcc/config/mips/p5600.md
@@ -200,7 +200,7 @@
(define_insn_reservation "p5600_fpu_div" 17
(and (eq_attr "cpu" "p5600")
(eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt"))
- "p5600_fpu_long, p5600_fpu_apu*17")
+ "p5600_fpu_long, p5600_fpu_apu*10")
;; fcvt
(define_insn_reservation "p5600_fpu_fcvt" 4
diff --git a/gcc/config/mips/p6600.md b/gcc/config/mips/p6600.md
index c5e26727fb8..b11ce2f2ee4 100644
--- a/gcc/config/mips/p6600.md
+++ b/gcc/config/mips/p6600.md
@@ -203,7 +203,7 @@
(define_insn_reservation "p6600_fpu_div" 17
(and (eq_attr "cpu" "p6600")
(eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt"))
- "p6600_fpu_long, p6600_fpu_apu*17")
+ "p6600_fpu_long, p6600_fpu_apu*10")
;; fcvt
(define_insn_reservation "p6600_fpu_fcvt" 4
diff --git a/gcc/config/mips/xlp.md b/gcc/config/mips/xlp.md
index d17ceba6049..ead5c753c2d 100644
--- a/gcc/config/mips/xlp.md
+++ b/gcc/config/mips/xlp.md
@@ -98,17 +98,17 @@
(eq_attr "type" "imul3"))
"xlp_ex2,nothing*2,xlp_ex2_wrb")
-(define_insn_reservation "ir_xlp_div" 24
+(define_insn_reservation "ir_xlp_div" 20
(and (eq_attr "cpu" "xlp")
(eq_attr "mode" "SI")
(eq_attr "type" "idiv"))
- "xlp_ex2+xlp_div,xlp_div*23,xlp_ex2_wrb")
+ "xlp_ex2+xlp_div,xlp_div*10,xlp_ex2_wrb")
-(define_insn_reservation "ir_xlp_ddiv" 48
+(define_insn_reservation "ir_xlp_ddiv" 20
(and (eq_attr "cpu" "xlp")
(eq_attr "mode" "DI")
(eq_attr "type" "idiv"))
- "xlp_ex2+xlp_div,xlp_div*47,xlp_ex2_wrb")
+ "xlp_ex2+xlp_div,xlp_div*10,xlp_ex2_wrb")
(define_insn_reservation "ir_xlp_store" 1
(and (eq_attr "cpu" "xlp")
@@ -179,17 +179,17 @@
(eq_attr "type" "fmadd"))
"xlp_fp,nothing*4,xlp_fp,nothing*4,xlp_fp_wrb")
-(define_insn_reservation "ir_xlp_fpcomplex_s" 23
+(define_insn_reservation "ir_xlp_fpcomplex_s" 20
(and (eq_attr "cpu" "xlp")
(eq_attr "mode" "SF")
(eq_attr "type" "fdiv,frdiv,frdiv1,frdiv2,fsqrt,frsqrt,frsqrt1,frsqrt2"))
- "xlp_fp+xlp_divsq,xlp_divsq*22,xlp_fp_wrb")
+ "xlp_fp+xlp_divsq,xlp_divsq*10,xlp_fp_wrb")
-(define_insn_reservation "ir_xlp_fpcomplex_d" 38
+(define_insn_reservation "ir_xlp_fpcomplex_d" 20
(and (eq_attr "cpu" "xlp")
(eq_attr "mode" "DF")
(eq_attr "type" "fdiv,frdiv,frdiv1,frdiv2,fsqrt,frsqrt,frsqrt1,frsqrt2"))
- "xlp_fp+xlp_divsq,xlp_divsq*37,xlp_fp_wrb")
+ "xlp_fp+xlp_divsq,xlp_divsq*10,xlp_fp_wrb")
(define_bypass 3 "ir_xlp_mul" "ir_xlp_mfhi")
@@ -207,7 +207,7 @@
;; (6) branch and ALU instruction.
;; The net result of this reservation is a big delay with flush of
;; ALU pipeline and outgoing reservations discouraging use of EX3.
-(define_insn_reservation "ir_xlp_sync_loop" 40
+(define_insn_reservation "ir_xlp_sync_loop" 20
(and (eq_attr "cpu" "xlp")
(eq_attr "type" "syncloop"))
- "(xlp_ex0+xlp_ex1+xlp_ex2+xlp_ex3)*39,xlp_ex3+(xlp_ex0|xlp_ex1|(xlp_ex2,xlp_ex2_wrb))")
+ "(xlp_ex0+xlp_ex1+xlp_ex2+xlp_ex3)*10,xlp_ex3+(xlp_ex0|xlp_ex1|(xlp_ex2,xlp_ex2_wrb))")
diff --git a/gcc/config/mips/xlr.md b/gcc/config/mips/xlr.md
index b2f1539a352..3c07f66aaaa 100644
--- a/gcc/config/mips/xlr.md
+++ b/gcc/config/mips/xlr.md
@@ -83,10 +83,10 @@
(eq_attr "type" "imul,imul3,imadd"))
"xlr_main_pipe,xlr_imuldiv_nopipe*6")
-(define_insn_reservation "ir_xlr_div" 68
+(define_insn_reservation "ir_xlr_div" 20
(and (eq_attr "cpu" "xlr")
(eq_attr "type" "idiv"))
- "xlr_main_pipe,xlr_imuldiv_nopipe*67")
+ "xlr_main_pipe,xlr_imuldiv_nopipe*10")
(define_insn_reservation "xlr_hilo" 2
(and (eq_attr "cpu" "xlr")
--
2.25.0
