> gcc/ChangeLog:
>
> PR target/97194
> * config/i386/i386-expand.c (ix86_expand_vector_set_var): New function.
> * config/i386/i386-protos.h (ix86_expand_vector_set_var): New Decl.
> * config/i386/predicates.md (vec_setm_operand): New predicate,
> true for const_int_operand or register_operand under TARGET_AVX2.
> * config/i386/sse.md (vec_set<mode>): Support both constant
> and variable index vec_set.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/avx2-vec-set-1.c: New test.
> * gcc.target/i386/avx2-vec-set-2.c: New test.
> * gcc.target/i386/avx512bw-vec-set-1.c: New test.
> * gcc.target/i386/avx512bw-vec-set-2.c: New test.
> * gcc.target/i386/avx512f-vec-set-2.c: New test.
> * gcc.target/i386/avx512vl-vec-set-2.c: New test.
+;; True for registers, or const_int_operand, used to vec_setm expander.
+(define_predicate "vec_setm_operand"
+ (ior (and (match_operand 0 "register_operand")
+ (match_test "TARGET_AVX2"))
+ (match_code "const_int")))
+
;; True for registers, or 1 or -1. Used to optimize double-word shifts.
(define_predicate "reg_or_pm1_operand"
(ior (match_operand 0 "register_operand")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index b153a87fb98..1798e5dea75 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -8098,11 +8098,14 @@ (define_insn "vec_setv2df_0"
(define_expand "vec_set<mode>"
[(match_operand:V 0 "register_operand")
(match_operand:<ssescalarmode> 1 "register_operand")
- (match_operand 2 "const_int_operand")]
+ (match_operand 2 "vec_setm_operand")]
You need to specify a mode, otherwise a register of any mode can pass here.
Uros.
