On Tue, Nov 10, 2020 at 4:18 PM Jeff Law via Gcc-patches < gcc-patches@gcc.gnu.org> wrote:
> > On 11/8/20 7:48 PM, HAO CHEN GUI via Gcc-patches wrote: > > ChangeLog > > > > * combine.c (combine_validate_cost): Add an argument for newi1pat. > > (try_combine): Add a 4-insn combine pattern for optimizing rtx > > sign_extend (op:zero_extend, zero_extend). > > It'd be nice to see motivating examples. Depending on their structure, > we may get better results cleaning things up with match.pd patterns. We > already have some which work in this space. > I don't have a use case for this specifically, but for the general case of allowing a 4-insn combine to split into 3 I do have a RISC-V use case for that in Philipp Tomsich's recent match.pd thread. https://gcc.gnu.org/pipermail/gcc-patches/2020-November/558765.html Maybe instead of modifying combine to know about the sign_extend(zero_extend zero_extend) case you could add a 4->3 splitter to the rs6000.md file, and then where we call combine_split_insns modify the code to accept 3 output insns when there were 4 input insns. That would fix this rs6000 case, and also allow me to fix my RISC-V case with a riscv.md splitter. Jim
