>> - CSR related instructions and fence instructions has to be splitted from
>> baseline ISA, zicsr and zifencei are corresponding sub-extension.
>
>
> It is actually only fence.i that is split off. fence is still part of the
> base ISA. This is why it is called zifencei.
Oh...I didn't notice that, thanks for the review.
>> diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
>> index 738556539f6..2aaa8e96451 100644
>> --- a/gcc/config/riscv/riscv.c
>> +++ b/gcc/config/riscv/riscv.c
>> @@ -3337,6 +3337,9 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model)
>> static bool
>> riscv_memmodel_needs_release_fence (enum memmodel model)
>> {
>> + if (!TARGET_ZIFENCEI)
>> + return false;
>> +
>> switch (model)
>> {
>> case MEMMODEL_ACQ_REL:
>
>
> This part looks wrong, as riscv_memmodel_needs_release_fence is only used for
> fence instructions, not for fence.i.
>>
>> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
>> index f15bad3b29e..756b35fb8c0 100644
>> --- a/gcc/config/riscv/riscv.md
>> +++ b/gcc/config/riscv/riscv.md
>> @@ -1543,19 +1543,20 @@
>> LCT_NORMAL, VOIDmode, operands[0], Pmode,
>> operands[1], Pmode, const0_rtx, Pmode);
>> #else
>> - emit_insn (gen_fence_i ());
>> + if (TARGET_ZIFENCEI)
>> + emit_insn (gen_fence_i ());
>> #endif
>> DONE;
>> })
>>
>> (define_insn "fence"
>> [(unspec_volatile [(const_int 0)] UNSPECV_FENCE)]
>> - ""
>> + "TARGET_ZIFENCEI"
>> "%|fence%-")
>>
>> (define_insn "fence_i"
>> [(unspec_volatile [(const_int 0)] UNSPECV_FENCE_I)]
>> - ""
>> + "TARGET_ZIFENCEI"
>> "fence.i")
>>
>> ;;
>
>
> The fence_i and clear_cache patterns are OK. The fence pattern change is
> wrong.
>
> You didn't change sync.md, but it only uses fence, so it needs no change.
>
> Jim
>
