Hi Segher, on 2020/11/27 上午5:11, Segher Boessenkool wrote: > Hi! > > On Thu, Nov 26, 2020 at 06:15:04PM +0800, Kewen.Lin wrote: >> During previous Power10 testing, I noticed that ISA 3.1 has >> dropped TM support. I think we should not generate TM >> related instructions for Power10 and later, or no? >> >> This patch is to turn off HTM support once we know the cpu >> setting is power10 or later, and warn something if the >> explicit option -mhtm is specified. > > We currently enable OPTION_MASK_HTM in ISA_2_7_MASKS_SERVER (in > rs6000-cpus.def), and include that in all later CPUs/archs. > > Could you fix it there instead? Easiest and most obvious is to just > add HTM to the power8, power9, and powerpc64le entries. >
Thanks for the comments! The attached patch followed your suggestion. Does it look better? Bootstrapped/regtested on powerpc64le-linux-gnu P8 and P10. BR, Kewen ----- gcc/ChangeLog: * config/rs6000/rs6000.c (rs6000_option_override_internal): Use OPTION_MASK_CRYPTO for Power8 target_enable check instead of OPTION_MASK_HTM. * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove OPTION_MASK_HTM. (RS6000_CPU): Add OPTION_MASK_HTM to power8, power9 and powerpc64le entries.
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 8d2c1ffd6cf..482e1b69dde 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -51,7 +51,6 @@ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DIRECT_MOVE \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ - | OPTION_MASK_HTM \ | OPTION_MASK_QUAD_MEMORY \ | OPTION_MASK_QUAD_MEMORY_ATOMIC) @@ -240,10 +239,13 @@ RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER) -RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) -RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER) +RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER + | OPTION_MASK_HTM) +RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER + | OPTION_MASK_HTM) RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) +RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER + | OPTION_MASK_HTM) RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index d8ac2f0cd2f..4f625d98078 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3807,7 +3807,8 @@ rs6000_option_override_internal (bool global_init_p) /* If little-endian, default to -mstrict-align on older processors. Testing for htm matches power8 and later. */ if (!BYTES_BIG_ENDIAN - && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM)) + && !(processor_target_table[tune_index].target_enable + & OPTION_MASK_CRYPTO)) rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN; if (!rs6000_fold_gimple)